Low-Area/Power Parallel FIR Digital Filter Implementations

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 17, Issue 1, 1997, Pages 75-92

  Parker, David A ^a,b,c   Parhi, Keshab K ^b,d,e,f  

^a Theseus Logic Inc   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

^c HOPE COLLEGE   (United States)

^d INDIAN INSTITUTE OF TECHNOLOGY   (India)

^e UNIVERSITY OF PENNSYLVANIA   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; SIGNAL FILTERING AND PREDICTION;

ADJACENT COEFFICIENT SHARING BASED SUBSTRUCTURE SHARING TECHNIQUE; PARALLEL FINITE IMPULSE RESPONSE (FIR) FILTERS; SCALABLE MAXIMUM ABSOLUTE DIFFERENCE (MAD) QUANTIZATION PROCESS;

DIGITAL FILTERS;

EID: 0031222835     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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