메뉴 건너뛰기




Volumn 2, Issue , 2002, Pages 801-808

Trends in reconfigurable logic and reconfigurable computing

Author keywords

[No Author keywords available]

Indexed keywords

NEW DIRECTIONS; RECONFIGURABLE COMPUTING; RECONFIGURABLE LOGIC;

EID: 77956444672     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046294     Document Type: Conference Paper
Times cited : (29)

References (64)
  • 3
    • 77956439392 scopus 로고    scopus 로고
    • (invited embedded tutorial) ASP-DAC'01, Yokohama, Japan, Jan 30 - Feb.
    • R. Hartenstein (invited embedded tutorial): Coarse Grain Reconfigurable Architectures; ASP-DAC'01, Yokohama, Japan, Jan 30 - Feb. 2, 2001
    • (2001) Coarse Grain Reconfigurable Architectures , vol.2
    • Hartenstein, R.1
  • 4
    • 0029488826 scopus 로고
    • Technology and business: Forces driving microprocessor evolution; Forces
    • Dec.
    • N. Tredennick: Technology and Business: Forces Driving Microprocessor Evolution; Proc. IEEE 83, 12 (Dec. 1995)
    • (1995) Proc. IEEE , vol.83 , pp. 12
    • Tredennick, N.1
  • 6
    • 77956425178 scopus 로고    scopus 로고
    • The roadmap to reconfigurable computing
    • R. Hartenstein, H. Grünbacher (Editors), Aug.; LNCS, Springer-Verlag 2000
    • R. Hartenstein, H. Grünbacher (Editors): The Roadmap to Reconfigurable computing - Proc. FPL2000, Aug. 27-30, 2000; LNCS, Springer-Verlag 2000
    • (2000) Proc. FPL2000 , pp. 27-30
  • 8
    • 4143078318 scopus 로고    scopus 로고
    • Reconfigurable computing: The roadmap to a new business model and its impact on SoC design; SBCCI 2001
    • (invited embedded tutorial:) Pirenopolis, DF, Brazil, September
    • R. Hartenstein (invited embedded tutorial:): Reconfigurable Computing: the Roadmap to a New Business Model and its Impact on SoC Design; SBCCI 2001 - 14th Symposium on Integrated Circuits and Systems Design, Pirenopolis, DF, Brazil, September 10-15, 2001
    • (2001) 14th Symposium on Integrated Circuits and Systems Design , pp. 10-15
    • Hartenstein, R.1
  • 9
    • 33646944543 scopus 로고    scopus 로고
    • Configurable systems-on-Chip: Commercial and academic approaches
    • Dubrovnik, Croatia, Sept
    • J. Becker: Configurable Systems-on-Chip: Commercial and Academic Approaches; ICECS 2002, Dubrovnik, Croatia, Sept 15-18, 2002
    • ICECS 2002 , vol.2002 , pp. 15-18
    • Becker, J.1
  • 11
    • 77956443998 scopus 로고    scopus 로고
    • Reconfigurable computing at Xilinx; DSD 2001
    • (keynote), Warsaw, Poland, Sep
    • S. Guccione (keynote): Reconfigurable Computing at Xilinx; DSD 2001, Digital System Design Symposium, Warsaw, Poland, Sep 4-6, 2001
    • (2001) Digital System Design Symposium , pp. 4-6
    • Guccione, S.1
  • 12
    • 0141942869 scopus 로고    scopus 로고
    • The microprocessor is no more general purpose (invited paper)
    • Austin,Texas, USA, Oct.
    • R. Hartenstein: The Microprocessor is no more General Purpose (invited paper), Proc. ISIS'97, Austin,Texas, USA, Oct. 8-10, 1997.
    • (1997) Proc. ISIS'97 , pp. 8-10
    • Hartenstein, R.1
  • 13
    • 0003849991 scopus 로고    scopus 로고
    • Reconfigurable architectures for general purpose computing
    • A. DeHon: Reconfigurable Architectures for General Purpose Computing; report no. AITR 1586, MIT AI Lab, 1996
    • (1996) Report No. AITR 1586, MIT AI Lab
    • Dehon, A.1
  • 15
    • 77956450549 scopus 로고    scopus 로고
    • http://pactcorp.com
  • 16
    • 77956426907 scopus 로고    scopus 로고
    • KressArray Xplorer: A New CAD environment to optimize reconfigurable datapath array architectures
    • Yokohama, Japan, Jan.
    • U. Nageldinger et al.: KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures; ASP-DAC, Yokohama, Japan, Jan. 25-28, 2000.
    • (2000) ASP-DAC , pp. 25-28
    • Nageldinger, U.1
  • 19
    • 33645163663 scopus 로고
    • Programmable arithmetic devices for digital signal processing
    • IEEE Press
    • D. Chen, J. Rabaey. PADDI: Programmable arithmetic devices for digital signal processing; #Digital Signal Processing IV, IEEE Press 1990
    • (1990) Digital Signal Processing IV
    • Chen, D.1    Rabaey. Paddi, J.2
  • 21
    • 77956422172 scopus 로고
    • MoM - A partly custom-design architecture compared to standard hardware
    • R. Hartenstein, A. Hirschbiel, M. Weber: MoM - a partly custom-design architecture compared to standard hardware; IEEE CompEuro 1989
    • (1989) IEEE CompEuro
    • Hartenstein, R.1    Hirschbiel, A.2    Weber, M.3
  • 22
    • 77956420679 scopus 로고    scopus 로고
    • (invited paper): über Szenen und Krisen; GI/ITG Workshop on Custom Computing Dagstuhl June
    • R. Hartenstein (invited paper): High-Performance Computing: über Szenen und Krisen; GI/ITG Workshop on Custom Computing, Dagstuhl, June 1996
    • (1996) High-Performance Computing
    • Hartenstein, R.1
  • 24
    • 77956429347 scopus 로고    scopus 로고
    • Stream-based arrays: Converging design flows for both reconfigurable and hardwired
    • (invited talk) December, Montpellier, France
    • R. Hartenstein (invited talk): Stream-based Arrays: Converging Design Flows for both, Reconfigurable and Hardwired .... ; IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2001), December 2-4,2001, Montpellier, France
    • (2001) IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2001) , pp. 2-4
    • Hartenstein, R.1
  • 25
    • 4444379887 scopus 로고    scopus 로고
    • Memory addressing organization for stream-based reconfigurable computing
    • Dubrovnik, Croatia, Sept
    • M. Herz, R. Hartenstein, M. Miranda, E. Brockmeyer, F. Catthoor: Memory Addressing Organization for Stream-based Reconfigurable Computing; ICECS 2002, Dubrovnik, Croatia, Sept 15-18, 2002
    • (2002) ICECS 2002 , pp. 15-18
    • Herz, M.1    Hartenstein, R.2    Miranda, M.3    Brockmeyer, E.4    Catthoor, F.5
  • 26
    • 77956425343 scopus 로고    scopus 로고
    • (invited post conference tutorial), Enabling Technologies for System-on-Chip Development November 21 Tampere, Finland
    • R. Hartenstein (invited post conference tutorial): on Enabling Technologies for Reconfigurable Computing 3rd Workshop.on Enabling Technologies for System-on-Chip Development November 21, 2001, Tampere, Finland
    • (2001) Enabling Technologies for Reconfigurable Computing 3rd Workshop
    • Hartenstein, R.1
  • 27
    • 0029529462 scopus 로고
    • A datapath synthesis system for the reconfigurable data-path architecture
    • Chiba, Japan, Aug. 29 - Sept.
    • R. Kress et al.: A Datapath Synthesis System for the Reconfigurable Data-path Architecture; ASP-DAC'95, Chiba, Japan, Aug. 29 - Sept. 1,1995
    • (1995) ASP-DAC'95 , vol.1
    • Kress, R.1
  • 31
    • 77956433928 scopus 로고    scopus 로고
    • (Editors), Tallinn, Estonia, Aug. 31-Sept., LNCS, Springer Verlag, 1998
    • R. Hartenstein, A. Keevallik (Editors): Proc. FPL'98, Tallinn, Estonia, Aug. 31-Sept. 3, 1998, LNCS, Springer Verlag, 1998
    • (1998) Proc. FPL'98 , vol.3
    • Hartenstein, R.1    Keevallik, A.2
  • 32
    • 77956430947 scopus 로고    scopus 로고
    • Fast compilation for pipelined reconfigurable fabrics
    • Monterey Feb.
    • M. Budiu and S. C. Goldstein: Fast Compilation for Pipelined Reconfigurable Fabrics; Proc. FPGA'99, Monterey, Feb. 1999, pp. 135-143.
    • (1999) Proc. FPGA'99 , pp. 135-143
    • Budiu, M.1    Goldstein, S.C.2
  • 33
    • 0033488527 scopus 로고    scopus 로고
    • Pipeline vectorization for reconfigurable systems
    • April
    • M. Weinhardt, W. Luk: Pipeline Vectorization for Reconfigurable Systems; Proc. IEEE FCCM, April 1999
    • (1999) Proc. IEEE FCCM
    • Weinhardt, M.1    Luk, W.2
  • 34
    • 85013607448 scopus 로고    scopus 로고
    • NAPA C: Compiling for a hybrid RISC / FPGA architecture
    • April
    • M. Gokhale, J. Stone: NAPA C: Compiling for a hybrid RISC / FPGA architecture; Proc. IEEE FCCM April 1998
    • (1998) Proc. IEEE FCCM
    • Gokhale, M.1    Stone, J.2
  • 35
    • 0030416290 scopus 로고    scopus 로고
    • A general approach in system design integrating reconfigurable accelerators
    • Austin, TX, Oct.
    • J. Becker et al.: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. IEEE ISIS'96; Austin, TX, Oct. 9-11, 1996
    • (1996) Proc. IEEE ISIS'96 , pp. 9-11
    • Becker, J.1
  • 37
    • 77956446766 scopus 로고    scopus 로고
    • A novel sequencer hardware for application specific computing
    • Zurich Switzerland July
    • M. Herz, et al.: A Novel Sequencer Hardware for Application Specific Computing; Proc. ASAP'97, Zurich, Switzerland, July 14-16, 1997
    • (1997) Proc. ASAP'97 , pp. 14-16
    • Herz, M.1
  • 40
    • 0026189343 scopus 로고
    • A novel ASIC design approach based on a new machine paradigm
    • July
    • R. Hartenstein et. al.: A Novel ASIC Design Approach Based on a New Machine Paradigm; IEEE J.SSC, Volume 26, No.7, July 1991.
    • (1991) IEEE J.SSC , vol.26 , Issue.7
    • Hartenstein, R.1
  • 41
    • 77956442331 scopus 로고
    • A novel paradigm of parallel computation and its use to implement simple high performance hardware
    • 30th Anniversary of the Computer Society of Japan, Tokyo, Japan
    • R. Hartenstein et al.: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90, 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990.
    • (1990) InfoJapan'90
    • Hartenstein, R.1
  • 42
    • 38249013922 scopus 로고    scopus 로고
    • A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW
    • North Holland - invited reprint of [41]
    • R. Hartenstein, A. Hirschbiel, K. Schmidt, M. Weber A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW; Future Generation Computer Systems 7, 91/92, North Holland - invited reprint of [41]
    • Future Generation Computer Systems , vol.7 , Issue.91-92
    • Hartenstein, R.1    Hirschbiel, A.2    Schmidt, K.3    Weber, M.4
  • 44
    • 77956450214 scopus 로고
    • (Editors), Prague, Czech Republic, Sept., LNCS, Springer Verlag, 1994
    • R. Hartenstein, M. Servit (Editors): Proc. FPL'94, Prague, Czech Republic, Sept. 7-10, 1994, LNCS, Springer Verlag, 1994
    • (1994) Proc. FPL'94 , vol.7-10
    • Hartenstein, R.1    Servit, M.2
  • 46
    • 77956429037 scopus 로고    scopus 로고
    • Custom memory management methodology
    • F. Cathcor et al: Custom Memory Management Methodology; Kluwer, 1998
    • (1998) Kluwer
    • Cathcor, F.1
  • 47
    • 0005363452 scopus 로고    scopus 로고
    • Data-reuse exploration for low-power realization of multimedia applications on embedded cores
    • Kos Island Greece Oct
    • N. D. Zervas et al.: Data-Reuse Exploration for Low-Power Realization of Multimedia Applications on Embedded Cores; PATMOS'99, Kos Island, Greece, Oct 1999
    • (1999) PATMOS'99
    • Zervas, N.D.1
  • 48
    • 0001286148 scopus 로고    scopus 로고
    • Data-reuse and parallel embedded architectures for low-power real-time multimedia applications
    • see: [49]
    • D. Soudris et al.: Data-Reuse and Parallel Embedded Architectures for Low-Power Real-Time Multimedia Applications; PATMOS' 2000, see: [49]
    • (2000) PATMOS
    • Soudris, D.1
  • 49
    • 77956436734 scopus 로고    scopus 로고
    • (Editors); Göttingen, Germany Sept., LNCS, Springer Verlag, 2000
    • D. Soudris, P. Pirsch, E. Barke (Editors): Proc. PATMOS 2000; Göttingen, Germany Sept. 13 -15, 2000; LNCS, Springer Verlag, 2000
    • (2000) Proc. PATMOS 2000 , vol.13-15
    • Soudris, D.1    Pirsch, P.2    Barke, E.3
  • 50
    • 0004591770 scopus 로고    scopus 로고
    • Power efficient media processor design space exploration
    • New Orleans June
    • J. Kin et al.: Power Efficient Media Processor Design Space Exploration; Proc. DAC'99, New Orleans, June 21-25, 1999
    • (1999) Proc. DAC'99 , pp. 21-25
    • Kin, J.1
  • 51
    • 0034854946 scopus 로고    scopus 로고
    • Analytical exploration of power efficient data-reuse transformations on multimedia applications
    • Salt Lake City May
    • S. Kougra et al.: Analytical Exploration of Power Efficient Data-Reuse Transformations on Multimedia Applications; ICASSP'2001, Salt Lake City, May 2001
    • (2001) ICASSP'2001
    • Kougra, S.1
  • 52
    • 0032303141 scopus 로고    scopus 로고
    • Formalized methodology for data reuse exploration for low power hierarchical memory mappings
    • on VLSI Systems, Dec.
    • S. Wuytak et al.: Formalized Methodology for Data Reuse Exploration for Low Power Hierarchical Memory Mappings; IEEE Trans, on VLSI Systems, Dec. 1998
    • (1998) IEEE Trans
    • Wuytak, S.1
  • 53
    • 77956440644 scopus 로고
    • Loop and data transformations: A tutorial
    • Computer Systems Research Institute University of Toronto June
    • D. Kulkami, M. Stumm: Loop and Data Transformations: A tutorial; CSRI-337, Computer Systems Research Institute, University of Toronto, June 1993
    • (1993) CSRI-337
    • Kulkami, D.1    Stumm, M.2
  • 54
    • 0028722375 scopus 로고
    • Power analysis of embedded software: A first step towards software power minimization
    • on VLSI Systems, Dec.
    • V. Tiwari et al.: Power Analysis of Embedded Software: A First Step Towards Software Power Minimization; IEEE Trans, on VLSI Systems, Dec. 1994
    • (1994) IEEE Trans
    • Tiwari, V.1
  • 55
    • 77956421164 scopus 로고    scopus 로고
    • Power analysis of the ARM 7 embedded microprocessor
    • Kos Island, Greece, Oct
    • G. Sinevriotis et al.: Power Analysis of the ARM 7 Embedded Microprocessor, PATMOS'99, Kos Island, Greece, Oct 1999
    • (1999) PATMOS'99
    • Sinevriotis, G.1
  • 56
    • 16244380727 scopus 로고    scopus 로고
    • Global multimedia design exploration using accurate memory organization feedback
    • A. Vandecapelle et al.: Global Multimedia Design Exploration using Accurate Memory organization Feedback; Proc. DAC 1999
    • (1999) Proc. DAC
    • Vandecapelle, A.1
  • 57
    • 84893700329 scopus 로고    scopus 로고
    • Dynamic algorithms for minimizing memory bandwidth in high throughput telecom and multimedia
    • Éditions Hermes
    • T. Omnès et al: Dynamic Algorithms for Minimizing Memory Bandwidth in High throughput Telecom and Multimedia; in: Techniques de Parallelization Automatique, TSI, Éditions Hermes, 1999
    • (1999) Techniques de Parallelization Automatique, TSI
    • Omnès, T.1
  • 58
    • 0033279857 scopus 로고    scopus 로고
    • Minimizing the required memory bandwidth in vlsi system realizations
    • VLSI Systems Dec.
    • S. Wuytack et al: Minimizing the required Memory Bandwidth in VLSI System Realizations; IEEE Trans. VLSI Systems, Dec. 1999
    • (1999) IEEE Trans
    • Wuytack, S.1
  • 63
    • 77956438375 scopus 로고    scopus 로고
    • (invited keynote) Jim - but not as we know it! Market Opportunities for the new Commercial Architectures; in [6]
    • T. Kean (invited keynote): It's FPL, Jim - but not as we know it! Market Opportunities for the new Commercial Architectures; in [6]
    • It's FPL
    • Kean, T.1
  • 64
    • 84969579902 scopus 로고    scopus 로고
    • Reconfigurable computing: A New Business Model - And its Impact on SoC Design
    • (invited keynote), Poland, Sept4 - 6
    • R. Hartenstein (invited keynote): Reconfigurable Computing: a New Business Model - and its Impact on SoC Design; DSD'2001 Warsaw, Poland, Sept4 - 6, 2001
    • (2001) DSD'2001 Warsaw
    • Hartenstein, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.