-
3
-
-
77956439392
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(invited embedded tutorial) ASP-DAC'01, Yokohama, Japan, Jan 30 - Feb.
-
R. Hartenstein (invited embedded tutorial): Coarse Grain Reconfigurable Architectures; ASP-DAC'01, Yokohama, Japan, Jan 30 - Feb. 2, 2001
-
(2001)
Coarse Grain Reconfigurable Architectures
, vol.2
-
-
Hartenstein, R.1
-
4
-
-
0029488826
-
Technology and business: Forces driving microprocessor evolution; Forces
-
Dec.
-
N. Tredennick: Technology and Business: Forces Driving Microprocessor Evolution; Proc. IEEE 83, 12 (Dec. 1995)
-
(1995)
Proc. IEEE
, vol.83
, pp. 12
-
-
Tredennick, N.1
-
6
-
-
77956425178
-
The roadmap to reconfigurable computing
-
R. Hartenstein, H. Grünbacher (Editors), Aug.; LNCS, Springer-Verlag 2000
-
R. Hartenstein, H. Grünbacher (Editors): The Roadmap to Reconfigurable computing - Proc. FPL2000, Aug. 27-30, 2000; LNCS, Springer-Verlag 2000
-
(2000)
Proc. FPL2000
, pp. 27-30
-
-
-
8
-
-
4143078318
-
Reconfigurable computing: The roadmap to a new business model and its impact on SoC design; SBCCI 2001
-
(invited embedded tutorial:) Pirenopolis, DF, Brazil, September
-
R. Hartenstein (invited embedded tutorial:): Reconfigurable Computing: the Roadmap to a New Business Model and its Impact on SoC Design; SBCCI 2001 - 14th Symposium on Integrated Circuits and Systems Design, Pirenopolis, DF, Brazil, September 10-15, 2001
-
(2001)
14th Symposium on Integrated Circuits and Systems Design
, pp. 10-15
-
-
Hartenstein, R.1
-
9
-
-
33646944543
-
Configurable systems-on-Chip: Commercial and academic approaches
-
Dubrovnik, Croatia, Sept
-
J. Becker: Configurable Systems-on-Chip: Commercial and Academic Approaches; ICECS 2002, Dubrovnik, Croatia, Sept 15-18, 2002
-
ICECS 2002
, vol.2002
, pp. 15-18
-
-
Becker, J.1
-
11
-
-
77956443998
-
Reconfigurable computing at Xilinx; DSD 2001
-
(keynote), Warsaw, Poland, Sep
-
S. Guccione (keynote): Reconfigurable Computing at Xilinx; DSD 2001, Digital System Design Symposium, Warsaw, Poland, Sep 4-6, 2001
-
(2001)
Digital System Design Symposium
, pp. 4-6
-
-
Guccione, S.1
-
12
-
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0141942869
-
The microprocessor is no more general purpose (invited paper)
-
Austin,Texas, USA, Oct.
-
R. Hartenstein: The Microprocessor is no more General Purpose (invited paper), Proc. ISIS'97, Austin,Texas, USA, Oct. 8-10, 1997.
-
(1997)
Proc. ISIS'97
, pp. 8-10
-
-
Hartenstein, R.1
-
13
-
-
0003849991
-
Reconfigurable architectures for general purpose computing
-
A. DeHon: Reconfigurable Architectures for General Purpose Computing; report no. AITR 1586, MIT AI Lab, 1996
-
(1996)
Report No. AITR 1586, MIT AI Lab
-
-
Dehon, A.1
-
15
-
-
77956450549
-
-
http://pactcorp.com
-
-
-
-
16
-
-
77956426907
-
KressArray Xplorer: A New CAD environment to optimize reconfigurable datapath array architectures
-
Yokohama, Japan, Jan.
-
U. Nageldinger et al.: KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures; ASP-DAC, Yokohama, Japan, Jan. 25-28, 2000.
-
(2000)
ASP-DAC
, pp. 25-28
-
-
Nageldinger, U.1
-
19
-
-
33645163663
-
Programmable arithmetic devices for digital signal processing
-
IEEE Press
-
D. Chen, J. Rabaey. PADDI: Programmable arithmetic devices for digital signal processing; #Digital Signal Processing IV, IEEE Press 1990
-
(1990)
Digital Signal Processing IV
-
-
Chen, D.1
Rabaey. Paddi, J.2
-
20
-
-
77956449334
-
The biggascale emulation engine; FPGA 2002
-
CA, Feb 24-26
-
C. Chang, K. Kuusilinna, R. Broderson, G. Wright; The Biggascale Emulation Engine; FPGA 2002, 10th Int'l Symp. on Field-programmable Gate Arrays; Monterey, CA, Feb 24 - 26, 2002
-
(2002)
10th Int'l Symp. on Field-programmable Gate Arrays; Monterey
-
-
Chang, C.1
Kuusilinna, K.2
Broderson, R.3
Wright, G.4
-
21
-
-
77956422172
-
MoM - A partly custom-design architecture compared to standard hardware
-
R. Hartenstein, A. Hirschbiel, M. Weber: MoM - a partly custom-design architecture compared to standard hardware; IEEE CompEuro 1989
-
(1989)
IEEE CompEuro
-
-
Hartenstein, R.1
Hirschbiel, A.2
Weber, M.3
-
22
-
-
77956420679
-
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(invited paper): über Szenen und Krisen; GI/ITG Workshop on Custom Computing Dagstuhl June
-
R. Hartenstein (invited paper): High-Performance Computing: über Szenen und Krisen; GI/ITG Workshop on Custom Computing, Dagstuhl, June 1996
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(1996)
High-Performance Computing
-
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Hartenstein, R.1
-
24
-
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77956429347
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Stream-based arrays: Converging design flows for both reconfigurable and hardwired
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(invited talk) December, Montpellier, France
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R. Hartenstein (invited talk): Stream-based Arrays: Converging Design Flows for both, Reconfigurable and Hardwired .... ; IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2001), December 2-4,2001, Montpellier, France
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(2001)
IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2001)
, pp. 2-4
-
-
Hartenstein, R.1
-
25
-
-
4444379887
-
Memory addressing organization for stream-based reconfigurable computing
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Dubrovnik, Croatia, Sept
-
M. Herz, R. Hartenstein, M. Miranda, E. Brockmeyer, F. Catthoor: Memory Addressing Organization for Stream-based Reconfigurable Computing; ICECS 2002, Dubrovnik, Croatia, Sept 15-18, 2002
-
(2002)
ICECS 2002
, pp. 15-18
-
-
Herz, M.1
Hartenstein, R.2
Miranda, M.3
Brockmeyer, E.4
Catthoor, F.5
-
26
-
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77956425343
-
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(invited post conference tutorial), Enabling Technologies for System-on-Chip Development November 21 Tampere, Finland
-
R. Hartenstein (invited post conference tutorial): on Enabling Technologies for Reconfigurable Computing 3rd Workshop.on Enabling Technologies for System-on-Chip Development November 21, 2001, Tampere, Finland
-
(2001)
Enabling Technologies for Reconfigurable Computing 3rd Workshop
-
-
Hartenstein, R.1
-
27
-
-
0029529462
-
A datapath synthesis system for the reconfigurable data-path architecture
-
Chiba, Japan, Aug. 29 - Sept.
-
R. Kress et al.: A Datapath Synthesis System for the Reconfigurable Data-path Architecture; ASP-DAC'95, Chiba, Japan, Aug. 29 - Sept. 1,1995
-
(1995)
ASP-DAC'95
, vol.1
-
-
Kress, R.1
-
31
-
-
77956433928
-
-
(Editors), Tallinn, Estonia, Aug. 31-Sept., LNCS, Springer Verlag, 1998
-
R. Hartenstein, A. Keevallik (Editors): Proc. FPL'98, Tallinn, Estonia, Aug. 31-Sept. 3, 1998, LNCS, Springer Verlag, 1998
-
(1998)
Proc. FPL'98
, vol.3
-
-
Hartenstein, R.1
Keevallik, A.2
-
32
-
-
77956430947
-
Fast compilation for pipelined reconfigurable fabrics
-
Monterey Feb.
-
M. Budiu and S. C. Goldstein: Fast Compilation for Pipelined Reconfigurable Fabrics; Proc. FPGA'99, Monterey, Feb. 1999, pp. 135-143.
-
(1999)
Proc. FPGA'99
, pp. 135-143
-
-
Budiu, M.1
Goldstein, S.C.2
-
33
-
-
0033488527
-
Pipeline vectorization for reconfigurable systems
-
April
-
M. Weinhardt, W. Luk: Pipeline Vectorization for Reconfigurable Systems; Proc. IEEE FCCM, April 1999
-
(1999)
Proc. IEEE FCCM
-
-
Weinhardt, M.1
Luk, W.2
-
34
-
-
85013607448
-
NAPA C: Compiling for a hybrid RISC / FPGA architecture
-
April
-
M. Gokhale, J. Stone: NAPA C: Compiling for a hybrid RISC / FPGA architecture; Proc. IEEE FCCM April 1998
-
(1998)
Proc. IEEE FCCM
-
-
Gokhale, M.1
Stone, J.2
-
35
-
-
0030416290
-
A general approach in system design integrating reconfigurable accelerators
-
Austin, TX, Oct.
-
J. Becker et al.: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. IEEE ISIS'96; Austin, TX, Oct. 9-11, 1996
-
(1996)
Proc. IEEE ISIS'96
, pp. 9-11
-
-
Becker, J.1
-
37
-
-
77956446766
-
A novel sequencer hardware for application specific computing
-
Zurich Switzerland July
-
M. Herz, et al.: A Novel Sequencer Hardware for Application Specific Computing; Proc. ASAP'97, Zurich, Switzerland, July 14-16, 1997
-
(1997)
Proc. ASAP'97
, pp. 14-16
-
-
Herz, M.1
-
39
-
-
77956424395
-
MOM - Map oriented machine
-
E. Chiricozzi, A. D'Amico, North-Holland
-
R. Hartenstein, A. Hirschbiel, M. Weber. MOM - Map Oriented Machine; in: E. Chiricozzi, A. D'Amico: Parallel Processing and Applications, North-Holland, 1988
-
(1988)
Parallel Processing and Applications
-
-
Hartenstein, R.1
Hirschbiel, A.2
Weber., M.3
-
40
-
-
0026189343
-
A novel ASIC design approach based on a new machine paradigm
-
July
-
R. Hartenstein et. al.: A Novel ASIC Design Approach Based on a New Machine Paradigm; IEEE J.SSC, Volume 26, No.7, July 1991.
-
(1991)
IEEE J.SSC
, vol.26
, Issue.7
-
-
Hartenstein, R.1
-
41
-
-
77956442331
-
A novel paradigm of parallel computation and its use to implement simple high performance hardware
-
30th Anniversary of the Computer Society of Japan, Tokyo, Japan
-
R. Hartenstein et al.: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90, 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990.
-
(1990)
InfoJapan'90
-
-
Hartenstein, R.1
-
42
-
-
38249013922
-
A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW
-
North Holland - invited reprint of [41]
-
R. Hartenstein, A. Hirschbiel, K. Schmidt, M. Weber A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW; Future Generation Computer Systems 7, 91/92, North Holland - invited reprint of [41]
-
Future Generation Computer Systems
, vol.7
, Issue.91-92
-
-
Hartenstein, R.1
Hirschbiel, A.2
Schmidt, K.3
Weber, M.4
-
43
-
-
84893687425
-
-
in [44]
-
A. Ast, J. Becker, R. Hartenstein, R. Kress, H. Reinig, K. Schmidt: Data- procedural Languages for FPL-based Machines; in [44]
-
Data- Procedural Languages for FPL-based Machines
-
-
Ast, A.1
Becker, J.2
Hartenstein, R.3
Kress, R.4
Reinig, H.5
Schmidt, K.6
-
44
-
-
77956450214
-
-
(Editors), Prague, Czech Republic, Sept., LNCS, Springer Verlag, 1994
-
R. Hartenstein, M. Servit (Editors): Proc. FPL'94, Prague, Czech Republic, Sept. 7-10, 1994, LNCS, Springer Verlag, 1994
-
(1994)
Proc. FPL'94
, vol.7-10
-
-
Hartenstein, R.1
Servit, M.2
-
46
-
-
77956429037
-
Custom memory management methodology
-
F. Cathcor et al: Custom Memory Management Methodology; Kluwer, 1998
-
(1998)
Kluwer
-
-
Cathcor, F.1
-
47
-
-
0005363452
-
Data-reuse exploration for low-power realization of multimedia applications on embedded cores
-
Kos Island Greece Oct
-
N. D. Zervas et al.: Data-Reuse Exploration for Low-Power Realization of Multimedia Applications on Embedded Cores; PATMOS'99, Kos Island, Greece, Oct 1999
-
(1999)
PATMOS'99
-
-
Zervas, N.D.1
-
48
-
-
0001286148
-
Data-reuse and parallel embedded architectures for low-power real-time multimedia applications
-
see: [49]
-
D. Soudris et al.: Data-Reuse and Parallel Embedded Architectures for Low-Power Real-Time Multimedia Applications; PATMOS' 2000, see: [49]
-
(2000)
PATMOS
-
-
Soudris, D.1
-
49
-
-
77956436734
-
-
(Editors); Göttingen, Germany Sept., LNCS, Springer Verlag, 2000
-
D. Soudris, P. Pirsch, E. Barke (Editors): Proc. PATMOS 2000; Göttingen, Germany Sept. 13 -15, 2000; LNCS, Springer Verlag, 2000
-
(2000)
Proc. PATMOS 2000
, vol.13-15
-
-
Soudris, D.1
Pirsch, P.2
Barke, E.3
-
50
-
-
0004591770
-
Power efficient media processor design space exploration
-
New Orleans June
-
J. Kin et al.: Power Efficient Media Processor Design Space Exploration; Proc. DAC'99, New Orleans, June 21-25, 1999
-
(1999)
Proc. DAC'99
, pp. 21-25
-
-
Kin, J.1
-
51
-
-
0034854946
-
Analytical exploration of power efficient data-reuse transformations on multimedia applications
-
Salt Lake City May
-
S. Kougra et al.: Analytical Exploration of Power Efficient Data-Reuse Transformations on Multimedia Applications; ICASSP'2001, Salt Lake City, May 2001
-
(2001)
ICASSP'2001
-
-
Kougra, S.1
-
52
-
-
0032303141
-
Formalized methodology for data reuse exploration for low power hierarchical memory mappings
-
on VLSI Systems, Dec.
-
S. Wuytak et al.: Formalized Methodology for Data Reuse Exploration for Low Power Hierarchical Memory Mappings; IEEE Trans, on VLSI Systems, Dec. 1998
-
(1998)
IEEE Trans
-
-
Wuytak, S.1
-
53
-
-
77956440644
-
Loop and data transformations: A tutorial
-
Computer Systems Research Institute University of Toronto June
-
D. Kulkami, M. Stumm: Loop and Data Transformations: A tutorial; CSRI-337, Computer Systems Research Institute, University of Toronto, June 1993
-
(1993)
CSRI-337
-
-
Kulkami, D.1
Stumm, M.2
-
54
-
-
0028722375
-
Power analysis of embedded software: A first step towards software power minimization
-
on VLSI Systems, Dec.
-
V. Tiwari et al.: Power Analysis of Embedded Software: A First Step Towards Software Power Minimization; IEEE Trans, on VLSI Systems, Dec. 1994
-
(1994)
IEEE Trans
-
-
Tiwari, V.1
-
55
-
-
77956421164
-
Power analysis of the ARM 7 embedded microprocessor
-
Kos Island, Greece, Oct
-
G. Sinevriotis et al.: Power Analysis of the ARM 7 Embedded Microprocessor, PATMOS'99, Kos Island, Greece, Oct 1999
-
(1999)
PATMOS'99
-
-
Sinevriotis, G.1
-
56
-
-
16244380727
-
Global multimedia design exploration using accurate memory organization feedback
-
A. Vandecapelle et al.: Global Multimedia Design Exploration using Accurate Memory organization Feedback; Proc. DAC 1999
-
(1999)
Proc. DAC
-
-
Vandecapelle, A.1
-
57
-
-
84893700329
-
Dynamic algorithms for minimizing memory bandwidth in high throughput telecom and multimedia
-
Éditions Hermes
-
T. Omnès et al: Dynamic Algorithms for Minimizing Memory Bandwidth in High throughput Telecom and Multimedia; in: Techniques de Parallelization Automatique, TSI, Éditions Hermes, 1999
-
(1999)
Techniques de Parallelization Automatique, TSI
-
-
Omnès, T.1
-
58
-
-
0033279857
-
Minimizing the required memory bandwidth in vlsi system realizations
-
VLSI Systems Dec.
-
S. Wuytack et al: Minimizing the required Memory Bandwidth in VLSI System Realizations; IEEE Trans. VLSI Systems, Dec. 1999
-
(1999)
IEEE Trans
-
-
Wuytack, S.1
-
59
-
-
0023400418
-
A flexible architecture for image processing
-
R.W. Hartenstein, AG. Hirschbiel, M. Weber. A Flexible Architecture for Image Processing; Microprocessing and Microprogramming, vol 21, pp 65-72,1987
-
(1987)
Microprocessing and Microprogramming
, vol.21
, pp. 65-72
-
-
Hartenstein, R.W.1
Hirschbiel, A.G.2
Weber, M.3
-
60
-
-
77956441234
-
A novel ASIC design approach based on a new machine paradigm
-
Grenoble, France
-
R. Hartenstein, A. Hirschbiel, K. Schmidt, M. Weber A Novel ASIC Design Approach based on a New Machine Paradigm; PRoc. ESSCIRC90, Grenoble, France
-
PRoc. ESSCIRC90
-
-
Hartenstein, R.1
Hirschbiel, A.2
Schmidt, K.3
Weber, M.4
-
61
-
-
84874178609
-
A high performance machine paradigm based on auto-sequencing data memory
-
Koloa, Hawaii
-
R. Harteastein, A. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS- 24, Hawaii Int' l. Conference on System Sciences, Koloa, Hawaii, 1991
-
(1991)
HICSS- 24, Hawaii Int' L. Conference on System Sciences
-
-
Harteastein, R.1
Hirschbiel, A.2
Riedmüller, M.3
Schmidt, K.4
Weber, M.5
-
63
-
-
77956438375
-
-
(invited keynote) Jim - but not as we know it! Market Opportunities for the new Commercial Architectures; in [6]
-
T. Kean (invited keynote): It's FPL, Jim - but not as we know it! Market Opportunities for the new Commercial Architectures; in [6]
-
It's FPL
-
-
Kean, T.1
-
64
-
-
84969579902
-
Reconfigurable computing: A New Business Model - And its Impact on SoC Design
-
(invited keynote), Poland, Sept4 - 6
-
R. Hartenstein (invited keynote): Reconfigurable Computing: a New Business Model - and its Impact on SoC Design; DSD'2001 Warsaw, Poland, Sept4 - 6, 2001
-
(2001)
DSD'2001 Warsaw
-
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Hartenstein, R.1
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