No flow underfill assembly process development for fine pitch flip chip silicon to silicon wafer level integration

Advancing Microelectronics

Volumn 37, Issue 4, 2010, Pages 20-25

  Li, Zhaozhi ^c   Lee, Sangil ^d   Lewis, Brian J ^a   Houston, Paul N ^a   Baldwin, Daniel F ^d   Stout, Eugene A ^b   Tessier, Theodore G ^b   Evans, John L ^c  

^a ENGENT Inc   (United States)

^b FlipChip International LLC   (United States)

^c AUBURN UNIVERSITY   (United States)

^d GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Chip floating; Flip chip; No flow Underfill; Silicon to on silicon; Underfill voiding; Wafer level packaging

Indexed keywords

CHIP FLOATING; FLIP CHIP; NO-FLOW UNDERFILL; UNDERFILL VOIDING; WAFER LEVEL PACKAGING;

APPROXIMATION THEORY; CHIP SCALE PACKAGES; COST REDUCTION; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; PACKAGING; SEMICONDUCTING SILICON COMPOUNDS; THREE DIMENSIONAL;

SILICON WAFERS;

EID: 77955528113     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. Yoon, S. W., Ganesh, V. P., et al., "Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application," IEEE Transactions on Advanced Packaging, Vol.31, No.3 (2008), pp. 519-526.
2. Topol, A. W., et al., "Three-dimensional integrated circuits," IBM Journal of Research and Development. Vol. 50, No. 4/5, July/September, 2006, pp. 491-506.
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5. Li, Z., Houston, P. N., Baldwin, D. F., Stout, G., Tessier, T., Evans, J.L., "Design, processing and reliability characterizations of a 3D-WLCSP packaged component," Proceedings of 59th Electronic Components and Technology Conference, San Diego, CA, May, 2009.
6. Houston, P. N., Li, Z., Baldwin, D. F., Stout, G., Tessier, T., "A 3DWLCSP Package Technology: Processing and Reliability Characterization," Proceedings of 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, May, 2008.
7. Stout, G., Tessier, T., Houston, P. N., Baldwin, D. F., Li, Z., "3D-WLCSP Package Technology: Technology and Design Considerations," 5th International Wafer-Level Packaging Conference, San Jose, CA, October, 2008.
8. Thorpe, R., Baldwin, D.F., "Yield analysis and process modeling of low cost, high throughput flip chip assembly based on no-flow underfill materials," IEEE Transactions on Electronics Packaging Manufacturing, Volume 24, Issue 2, pp. 123-135.
9. Sangil Lee, Myung Jin Yim, Master, R.N., Wong, C.P., Baldwin, D.F., "Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill," IEEE Transactions on Electronics Packaging Manufacturing, Volume 32, Issue 2, pp. 106-114.