3D interconnection process development and integration with low stress TSV

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 798-802

  Chua, T T ^a   Ho, S W ^a   Li, H Y ^a   Khong, C H ^a   Liao, E B ^a   Chew, S P ^a   Lee, W S ^a   Lim, L S ^a   Pang, X F ^a   Kriangsak, S L ^b   Ng, C ^b   Nathapong, S ^b   Toh, C H ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b United Test and Assembly Center Ltd UTAC   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

3D INTERCONNECT; BENDING STRESS; LOW STRESS; MECHANICAL SIMULATIONS; POLYMER FILLING; PROCESS DEVELOPMENT; PROCESS STEPS; REMOVAL PROCESS; WAFER WARPAGE;

CHEMICAL MECHANICAL POLISHING; CHEMICAL POLISHING; FILLING; INTEGRATED CIRCUITS; POLYMERS; SILICON WAFERS; STRESSES; TECHNOLOGY; THREE DIMENSIONAL;

FILLED POLYMERS;

EID: 77955211800     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490728     Document Type: Conference Paper

References (9)

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