3D TSV processes and its assembly/packaging technology

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Yoon, Seung Wook ^a   Yang, Dae Wook ^b   Koo, Jae Hoon ^a   Padmanathan, Meenakshi ^c   Carson, Flynn ^c  

^a STATS CHIPPAC LTD   (Singapore)

^b STATS ChipPAC Korea Ltd   (South Korea)

^c STATS ChipPAC Ltd   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTERCONNECTS; 3D PACKAGING; 3D STACKING; ADVANCED PACKAGING; CHIP STACKING; ELECTRONIC PRODUCT; FABRICATION PROCESS; FORM FACTORS; MATERIALS AND PROCESS; MICRO-BUMPS; OVERALL COSTS; POWER CONSUMPTION; POWER DISSIPATION; PROCESS STEPS; RESEARCH INSTITUTES; SEMICONDUCTOR INDUSTRY; SEMICONDUCTOR MANUFACTURERS; SIGNAL SPEED; THIN WAFERS; THROUGH-SILICON-VIA; ULTRA FINE PITCH;

APPROXIMATION THEORY; COMPUTER CRIME; ELECTRIC POWER UTILIZATION; ELECTRONICS INDUSTRY; PACKAGING; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL; WAFER BONDING;

CHIP SCALE PACKAGES;

EID: 70549105980     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306535     Document Type: Conference Paper

References (7)

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3. th Electronic Packaging Technology Conference 2008, 11-14 Dec 2008, Singapore
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