3D integration technology for set-top box application

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Henry, D ^a   Cheramy, S ^a   Charbonnier, J ^a   Chausse, P ^a   Neyret, M ^a   Brunet Manquat, C ^a   Verrun, S ^a   Sillon, N ^a   Bonnot, L ^b   Gagnard, X ^b   Saugier, E ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Stacking back side connections; Trough silicon vias (TSV); Wafer level packaging

Indexed keywords

3-D INTEGRATION; 45NM TECHNOLOGY; CHIP STACKING; HIGH ASPECT RATIO; PROCESS FLOWS; SET TOP BOX; SPECIFIC TEST VEHICLE; TROUGH SILICON VIAS (TSV); WAFER LEVEL PACKAGING; WAFER-LEVEL PACKAGING TECHNOLOGY;

ASPECT RATIO; BUILDING MATERIALS; CHIP SCALE PACKAGES; DEBONDING; INTERCONNECTION NETWORKS; NANOTECHNOLOGY; PACKAGING; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 70549092968     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306561     Document Type: Conference Paper

References (8)

1. L. Bonnot & Al, "3D integration program overview", DATE 2009, April 2009.
2. A. Jouve & Al, "Facilitating Ultrathin Wafer Handling for TSV Processing", EPTC 2008, 9-12 december 2008, Singapour.
3. J. Charbonnier & Al, "Integration of a temporary carrier in a TSV Process Flow", EC TC 2009, 26-29 May 2009
4. Ho-Young Son & Al, "Cu/SnAg Double Bump Flip Chip Assembly as an Alternative of Solder Flip Chipon Organic Substrates for Fine Pitch Applications", 2007 ECTC Conference, Reno (NE), p. 864-871.
5. B. Ebersberger & Al, "Cu Pillar Bumps as a Lead-Free Drop-in Replacement for Solder-Bumped, Flip-Chip Interconnects", ECTC Conference 2008, Orlando (FL), p. 59-66.
6. D.Henry & Al, "Through silicon vias technology for cmos image sensors packaging: presentation of technology and electrical results", EPTC 2008, 9-12 december 2008, Singapour.
7. S. Pargfrieder & Al, "3D Integration by Through-Silicon-Via (TSV) processing enabled by Temporary Bonding and Debonding Technology", Advanced Packaging, April 2009 issue.
8. S. Cheramy & Al, "3D integration process flow for set-top box application: description of technology and electrical results", EMPC 2009, Rimini, Italy.