Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack

EuroSys'10 - Proceedings of the EuroSys 2010 Conference

Volumn , Issue , 2010, Pages 27-40

  Christie, Dave ^a   Chung, Jae Woong ^a   Diestelhorst, Stephan ^a   Hohmuth, Michael ^a   Pohlack, Martin ^a   Fetzer, Christof ^b   Nowack, Martin ^b   Riegel, Torvald ^b   Felber, Pascal ^c   Marlier, Patrick ^c   Rivière, Etienne ^c  

^a ADVANCED MICRO DEVICES   (United States)

^b DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^c UNIVERSITY OF NEUCHÂTEL   (Switzerland)

Author keywords

transactional memory

Indexed keywords

CAPACITY LIMITATION; CONCURRENT PROGRAM; CYCLE ACCURATE; INSTRUCTION SET EXTENSION; PERFORMANCE GAIN; SOFTWARE STACKS; SOFTWARE TRANSACTIONAL MEMORY; SPEED-UPS; TRANSACTIONAL MEMORY;

COMPUTER SOFTWARE SELECTION AND EVALUATION; PROGRAM COMPILERS; SYNCHRONIZATION;

STORAGE ALLOCATION (COMPUTER);

EID: 77954573319     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1755913.1755918     Document Type: Conference Paper

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