Modeling of cache access behavior based on Zipf's law

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 310, Issue , 2008, Pages 9-15

  Kotera, Isao ^a   Egawa, Ryusuke ^a   Takizawa, Hiroyuki ^a   Kobayashi, Hiroaki ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

cache memory; cache partitioning; Zipf's law

Indexed keywords

ACCURATE PREDICTION; BEHAVIOR-BASED; CACHE ACCESS; CACHE CAPACITY; CACHE PARTITIONING; CHIP MULTIPROCESSOR; DISTANCE DISTRIBUTIONS; HIGH-PERFORMANCE PROCESSING; MODEL-BASED; RESOURCE CONFLICT; SHARED CACHE; SHARED RESOURCES; ZIPF'S LAW;

MATHEMATICAL MODELS;

CACHE MEMORY;

EID: 77954453709     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1509084.1509086     Document Type: Conference Paper

References (18)

1. A. Bardine, P. Foglia, G. Gabrielli, C. A. Prete, and P. Stenström. Improving power efficiency of d-nuca caches. ACM SIGARCH Computer Architecture News, 35(4):53-58, Sept. 2007.
2. N. Binkert, R. Dreslinski, L. Hsu, K. Lim, A. Saidi, and S. Reinhardt. The m5 simulator: Modeling networked systems. IEEE Micro, 26(4):52-60, July-Aug. 2006.
3. L. Breslau, P. Cao, L. Fan, G. Phillips, and S. Shenker. Web caching and zipf-like distributions: evidence and implications. INFOCOM '99: Proceedings of the Eighteenth Annual Joint Conference, 1:126-134, Mar 1999.
4. D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting inter-thread cache contention on a chip multi-processor architecture. In HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pages 340-351, 2005.
5. C. Cunha, A. Bestavros, and M. Crovella. Characteristics of World Wide Web Client-based Traces. Technical Report BUCS-TR-1995-010, Boston University, CS Dept, Boston, MA 02215, April 1995.
6. D. G. Feitelson. On the interpretation of top500 data. International Journal of High Performance Computing Applications, 13(2):146-153, 1999.
7. B. Gutenberg and C. F. Richter. Frequency and energy of earthquakes. Seismicity of the Earth and Associated Phenomena, pages 17-19, 1954.
8. R. Iyer, L. Zhao, F. Guo, R. Illikkal, S. Makineni, D. Newell, Y. Solihin, L. Hsu, and S. Reinhardt. Qos policies and architecture for cache/memory in cmp platforms. Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 35(1):25-36, 2007.
9. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT '04: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 111-122, 2004.
10. H. Kobayashi, I. Kotera, and H. Takizawa. Locality analysis to control dynamically way-adaptable caches. ACM SIGARCH Computer Architecture News, 33(3):25-32, 2005.
11. I. Kotera, K. Abe, R. Egawa, H. Takizawa, and H. Kobayashi. Power-aware dynamic cache partitionning for cmps. Transactions on High-Performance Embedded Architectures and Compilers, 3(2):149-167, 2008.
12. I. Kotera, R. Egawa, H. Takizawa, and H. Kobayashi. A power-aware shared cache mechanism based on locality assessment of memory reference for cmps. In MEDEA '07: Proceedings of the 2007 workshop on MEmory performance, pages 113-120, 2007.
13. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 423-432, 2006.
14. M. Ripeanu. Note on zipf distribution in top500 supercomputers list. Technical report, IEEE Distributed Systems Online, October 2006.
15. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. Journal of Supercomputing, 28(1):7-26, 2004.
16. The Standard Performance Evaluation Corporation. http://www.spec.org/.
17. TOP500 Supercomputer Sites. http://www.top500.org/.
18. G. K. Zipf. Human Behavior and the Principle of Least Effort. Addison-Wesley, 1949.