A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2007, Pages 113-120

  Kotera, Isao ^a   Egawa, Ryusuke ^a   Takizawa, Hiroyuki ^a   Kobayashi, Hiroaki ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MECHANISM; CACHE PARTITIONING; CHIP MULTIPROCESSORS; CONTROL POLICY; CYCLE-ACCURATE SIMULATORS; ENERGY CONSUMPTION; LOW POWER; MEMORY REFERENCES; MICROPROCESSOR DESIGNS; ON CHIPS; PARAMETER SETTING; PERFORMANCE DEGRADATION; PERFORMANCE EVALUATION; PERFORMANCE-ORIENTED PARAMETERS; POWER GATINGS; POWER REDUCTIONS; POWER-AWARE; SHARED CACHE;

MICROPROCESSOR CHIPS;

MACHINE DESIGN;

EID: 77954433044     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1327171.1327185     Document Type: Conference Paper

References (16)

1. D. Albonesi. Selective cache ways: on-demand cache resource allocation. In Microarchitecture, 1999. MICRO-32. Proceedings. 32nd Annual International Symposium on, pages 248-259, 16-18 Nov. 1999.
2. N. Binkert, R. Dreslinski, L. Hsu, K. Lim, A. Saidi, and S. Reinhardt. The m5 simulator: Modeling networked systems. Micro, IEEE, 26(4):52-60, July-Aug. 2006.
3. J. Butts and G. Sohi. A static power model for architects. In Microarchitecture, 2000. MICRO-33. Proceedings. 33rd Annual IEEE/ACM International Symposium on, pages 191-201, 10-13 Dec. 2000.
4. D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting inter-thread cache contention on a chip multi-processor architecture. In High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on, pages 340-351, 12-16 Feb. 2005.
5. K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: simple techniques for reducing leakage power. In Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on, pages 148-157, 25-29 May 2002.
6. S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. In Computer Architecture, 2001. Proceedings. 28th Annual International Symposium on, pages 240-251, 30 June-4 July 2001.
7. N. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and V. Narayanan. Leakage current: Moore's law meets static power. Computer, 36(12):68-75, Dec. 2003.
8. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT '04: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 111-122, Washington, DC, USA, 2004. IEEE Computer Society.
9. H. Kobayashi, I. Kotera, and H. Takizawa. Locality analysis to control dynamically way-adaptable caches. SIGARCH Comput. Archit. News, 33(3):25-32, 2005.
10. B. Nayfeh and K. Olukotun. A single-chip multiprocessor. Computer, 30(9):79-85, Sept. 1997.
11. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 423-432, Washington, DC, USA, 2006. IEEE Computer Society.
12. The standard performance evaluation corporation. http://www.spec.org/.
13. M. Stan and K. Skadron. Power-aware computing. Computer, 36(12):35-38, Dec. 2003.
14. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. Journal of Supercomputing, 28(1):7-26, 2004.
15. D. W. Wall. Limits of instruction-level parallelism. SIGARCH Comput. Archit. News, 19(2):176-188, 1991.
16. S. Wilton and N. Jouppi. Cacti: an enhanced cache access and cycle time model. Solid-State Circuits, IEEE Journal of, 31(5):677-688, May 1996.