High performance reconfigurable multi-processor-based computing on FPGAs

Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010

Volumn , Issue , 2010, Pages

  Göhringer, Diana ^a   Becker, Jürgen ^b  

^a FRAUNHOFER IOSB   (Germany)

^b KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

Design methodology; Dynamic and partial reconfiguration; Field Programmable Gate Array (FPGA); Image processing; Multiprocessor System On Chip (MPSoC)

Indexed keywords

ADAPTIVITY; COMPUTATIONAL PERFORMANCE; DESIGN METHODOLOGY; DYNAMIC AND PARTIAL RECONFIGURATION; HIGH PERFORMANCE COMPUTING; MANY-CORE; MEET-IN-THE-MIDDLE; MULTI-PROCESSORS; MULTIPROCESSOR SYSTEM ON CHIPS; NOVEL HARDWARE; RE-CONFIGURABLE; RUNTIMES; SILICON DIE; TASK MAPPING; TOPDOWN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATION THEORY; COMPUTER ARCHITECTURE; DISTRIBUTED PARAMETER NETWORKS; IMAGE PROCESSING; IMAGING SYSTEMS; LOGIC GATES; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; PROGRAMMABLE LOGIC CONTROLLERS;

MULTIPROCESSING SYSTEMS;

EID: 77954059823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2010.5470800     Document Type: Conference Paper

References (16)

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