Star-wheels network-on-chip featuring a self-adaptive mixed topology and a synergy of a circuit- and a packet-switching communication protocol

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 320-325

  Göhringer, Diana ^a   Liu, Bin ^a   Hübner, Michael ^b   Becker, Jürgen ^b  

^a FRAUNHOFER GESELLSCHAFT   (Germany)

^b UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

Dynamic and partial reconfiguration; FPGA; Image processing; Multiprocessor System on Chip (MPSoC); Network on Chip (NoC)

Indexed keywords

ACADEMIC INSTITUTIONS; APPLICATION SCENARIO; BUS-BASED; COMMUNICATION PROTOCOLS; COMPUTING ARCHITECTURE; DYNAMIC AND PARTIAL RECONFIGURATION; HARDWARE COST; HETEROGENEOUS COMMUNICATION; HIGH-PERFORMANCE COMPUTING APPLICATIONS; MULTIPLE PROCESSORS; MULTIPROCESSOR SYSTEM ON CHIPS; NETWORK ON CHIP; ON CHIP COMMUNICATION; ON CHIPS; PERFORMANCE DATA; PHYSICAL REALIZATION; PROCESSING ELEMENTS; RUNTIMES; SELF-ADAPTIVE; SWITCHED COMMUNICATIONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION; COMPUTATION THEORY; DATA PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; IMAGING SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK PROTOCOLS; PROGRAMMABLE LOGIC CONTROLLERS; TOPOLOGY;

ELECTRIC NETWORK TOPOLOGY;

EID: 70449884159     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272279     Document Type: Conference Paper

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