Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM

Volumn , Issue , 2008, Pages

  Hübner, Michael ^a   Braun, Lars ^a   Göhringer, Diana ^b   Becker, Jürgen ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

^b FRAUNHOFER GESELLSCHAFT   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; COMMUNICATION SYSTEMS; COMPUTER NETWORKS; COMPUTER SOFTWARE REUSABILITY; DISTRIBUTED PARAMETER NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SILICON; TECHNOLOGY; TELECOMMUNICATION NETWORKS;

MULTI-LAYER NETWORKS; PARTIAL RECONFIGURATION; RUN-TIME;

INTERNET PROTOCOLS;

EID: 51049089554     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2008.4536504     Document Type: Conference Paper

References (12)

1. Reiner Hartenstein: "Reconfigurable Technologies", Seminar at Department of Informatics, Kyushu University, Higashi-ku, Fukuoka City, Kyushu, Japan; July 23, 2004
2. Reiner Hartenstein: RC-Education paper
3. M. Ullmann, B. Grimm, M. Huebner, J. Becker: "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration", RAW04, Santa Fé, USA
4. L. Benini, G. De Micheli: "Networks on Chip: A New Paradigm for Systems on Chip Design", Date 02, March 3-7, Paris France
5. F. Worm, P. Ienne, P. Thiran, G. De Micheli: "An Adaptive Low Power Transmission Scheme for On-chip Networks", ISSS 02, October 2002, Kyoto Japan
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7. M. Huebner, M. Ullmann, L. Braun, A. Klausmann, J. Becker: "Scalable Application-dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems", FPL 2004, Antwerp, Belgium
8. M. Huebner, M. Ullmann, F. Weissel, J. Becker: "Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration", RAW04, Santa Fé, USA
9. "Two Flows for Partial Reconfiguration: Module Based or Difference Based", Xilinx XAPP290, November 25, 2003
10. M. Huebner, T. Becker, J. Becker "Real-Time LUT-Based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration", SBCCI04, Brasil
11. A. Jantsch, H. Tenhunen: "Networks on Chip", Kluwer 2003, ISBN: 1-4020-7392-5
12. Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, and Stefan Bach: "Circuit switched run-time adaptive network-on-chip for image processing applications". In Proc. International Conference on Field Programmable Logic and Applications FPL 2007, pages 688-691