CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures

Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010

Volumn , Issue , 2010, Pages

  Göhringer, Diana ^a   Hübner, Michael ^b   Zeutebouo, Etienne Nguepi ^a   Becker, Jürgen ^b  

^a FRAUNHOFER IOSB   (Germany)

^b KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

FPGA; MPSoC; Operating system; Reconfigurable computing; Scheduling; Task mapping

Indexed keywords

ACCESS PORTS; ACCESS SCHEDULING; DYNAMIC RE-CONFIGURATION; EMBEDDED PROCESSORS; HARDWARE ARCHITECTURE; HARDWARE BLOCKS; HARDWARE RESOURCES; INTERNAL CONFIGURATION ACCESS PORTS; MULTI PROCESSOR ARCHITECTURE; MULTI PROCESSOR SYSTEMS; MULTIPLE INSTANCES; OPERATING SYSTEMS; PRIORITY-BASED; RE-CONFIGURABLE; RECONFIGURABLE COMPUTING; RESOURCE MANAGEMENT; RUN-TIME SCHEDULING; RUNTIMES; SCHEDULING TASKS; SOFTWARE TASKS; TASK MAPPING; TASK-SCHEDULING;

COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; DISTRIBUTED PARAMETER NETWORKS; DYNAMIC MODELS; HARDWARE; MAPPING; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; NATURAL RESOURCES MANAGEMENT; PORTS AND HARBORS; RESOURCE ALLOCATION; SCHEDULING;

RECONFIGURABLE HARDWARE;

EID: 77954080043     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2010.5470732     Document Type: Conference Paper

References (13)

1. J. Blazewicz, K.H. Ecker, E. Pesch, G. Schmidt, J. Weglarz: "Scheduling Computer and Manufacturing Processes"; Berlin (Springer) 2001, ISBN 3-540-41931-4.
2. D. Göhringer, M. Hübner, V. Schatz, J. Becker: "Runtime Adaptive Multi-Processor System-on-Chip: RAMPSoC"; In Proc. of RAW 2008 at the IPDPS 2008, April 2008.
3. F. Dittman, S. Frank: "Hard Real-Time Reconfiguration Port Scheduling"; In Proc. of DATE 2007, p.123-128, April 2007.
4. M. Ullmann, M. Hübner, B. Grimm, J. Becker: "On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities"; In Proc. of FPL 2004, pp. 454-463, August 2004.
5. E. Lübbers, M. Platzer: "ReconOS: An RTOS supporting Hard- and Software Threads"; In Proc. of FPL 2007, August 2007.
6. D. Göhringer, M. Hübner, T. Perschke, J. Becker: "New Dimensions for Multiprocessor Architectures: On Demand Heterogeneity, Infrastructure and Performance through Reconfigurability: The RAMPSoC Approach"; In Proc. of FPL 2008, pp. 495-498, Sept. 2008.
7. "PowerPC Processor Reference Guide"; UG011 (v.1.2), Jan.19, 2007. Available at http://www.xilinx.com.
8. Alpha Data: http://www.alpha-data.com.
9. "Xilkernel v3-00-a"; EDK 9.1i, December 12, 2006. Available at http://www.xilinx.com.
10. "MicroBlaze Processor Reference Guide, Embedded Development Kit, EDK 9.2i", UG081 (v8.1). Available at http://www.xilinx.com.
11. "Fast Simplex Link (FSL) Bus (v2.11a)"; DS449, June 25, 2007. Available at http://www.xilinx.com.
12. O. Sander, L. Braun, M. Huebner, J. Becker: "Data Reallocation by Exploiting FPGA Configuration Mechanisms"; In Proc of ARC 2008, Springer Volume 4943/2008, March 2008.
13. C. Claus, B. Zhang, W. Stechele, L. Braun, M. Hübner, J. Becker: "A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput"; In Proc. of FPL 2008, Sept. 2008.