Effects of negative-bias operation and optical stress on sark current in CMOS image sensors

IEEE Transactions on Electron Devices

Volumn 57, Issue 7, 2010, Pages 1512-1518

  Watanabe, Takashi ^a   Park, Jong Ho ^a   Aoyama, Satoshi ^a   Isobe, Keigo ^a   Kawahito, Shoji ^b  

^a 10F   (Japan)

^b SHIZUOKA UNIVERSITY   (Japan)

Author keywords

CMOS image sensor (CIS); dark current; negative bias; optical stress; tunneling

Indexed keywords

BIAS OPERATION; CMOS IMAGE SENSOR; CMOS IMAGE SENSOR (CIS); EMISSION MECHANISM; HARDENING EFFECTS; MULTIPLE STRESS; NEGATIVE BIAS; NORMAL OPERATING CONDITIONS; OFF MODE; PHOTON-ASSISTED TUNNELING; THRESHOLD VOLTAGE SHIFTS; TRANSFER GATE; VISIBLE LIGHT; WELL STRUCTURE;

DARK CURRENTS; DIGITAL CAMERAS; DIGITAL IMAGE STORAGE; PIXELS; THRESHOLD VOLTAGE; TUNNELING (EXCAVATION);

IMAGE SENSORS;

EID: 77954030724     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2049220     Document Type: Article

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