Tracking uncertainty with probabilistic logic circuit testing

IEEE Design and Test of Computers

Volumn 24, Issue 4, 2007, Pages 312-321

  Krishnaswamy, Smita ^a   Markov, Igor L ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Fault modeling framework; Integer linear programming; Logic circuit testing; Probabilistic faults; Test vector sensitivity

Indexed keywords

FAULT-MODELING FRAMEWORK; INTEGER LINEAR PROGRAMMING; LOGIC CIRCUIT TESTING; PROBABILISTIC FAULTS; TEST-VECTOR SENSITIVITY;

COSMOLOGY; DATA COMPRESSION; DYNAMIC PROGRAMMING; ELECTRONIC CIRCUIT TRACKING; INTEGER PROGRAMMING; LINEAR PROGRAMMING; LINEARIZATION; OPTIMIZATION; PARTICLE SIZE ANALYSIS; PROBABILITY; SWITCHING CIRCUITS; TESTING; VECTORS;

LOGIC CIRCUITS;

EID: 49549090550     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.146     Document Type: Article

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