Optimization of wafer scale H-tree clock distribution network based on a new statistical skew model

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2000, Pages 96-104

  Jiang, Xiaohong ^a   Horiguchi, Susumu ^a  

^a JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK DISTRIBUTION NETWORKS; DISTRIBUTED COMPUTER SYSTEMS; MATHEMATICAL MODELS; OPTIMIZATION; PRINTED CIRCUIT DESIGN; STATISTICAL METHODS; TREES (MATHEMATICS);

CLOCK PERIOD; CLOCK SKEWS; CLOSED-FORM MODELS; H-TREES; MINIMISATION; NETWORK-BASED; OPTIMISATIONS; POWER RESTRICTIONS; WAFER SCALE; WELL BALANCED;

ELECTRIC CLOCKS; WSI CIRCUITS;

CLOCK DISTRIBUTION NETWORKS; CLOCK SKEW; SKEW MODELS;

EID: 0034517342     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2000.887147     Document Type: Article

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