The important challenge to extend spacer DP process towards 22nm and beyond

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7639, Issue , 2010, Pages

  Oyama, Kenichi ^a   Nishimura, Eiichi ^a   Kushibiki, Masato ^a   Hasebe, Kazuhide ^a   Nakajima, Shigeru ^a   Murakami, Hiroki ^a   Hara, Arisa ^a   Yamauchi, Shohei ^a   Natori, Sakurako ^a   Yabe, Kazuo ^a   Yamaji, Tomohito ^a   Nakatsuji, Ryota ^a   Yaegashi, Hidetami ^a  

^a TOKYO ELECTRON LTD   (Japan)

Author keywords

22nm node; double patterning; DRAM; LLE; logic; low temp SiO2; NAND; self aligned spacer process; sidewall transfer; spacer DP; SRAM; SWT; trim

Indexed keywords

32-NM NODE; DOUBLE PATTERNING; ETCHING MASKS; PROCESS COSTS; PROCESS STEPS; REPETITIVE PATTERN; SELF-ALIGNED;

MASKS;

NANOTECHNOLOGY;

EID: 77953495676     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.845970     Document Type: Conference Paper

References (7)

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