Process variation and NBTI tolerant standard cells to improve parametric yield and lifetime of ICs

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 291-296

  Basu, Shubhankar ^a   Vemuri, Ranga ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATH ANALYSIS; ELECTRIC BATTERIES; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; OPTIMIZATION;

NANOMETERS; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); PARAMETRIC YIELD; PMOS TRANSISTORS;

INTEGRATED CIRCUITS;

EID: 36348965239     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.85     Document Type: Conference Paper

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