-
1
-
-
34248645728
-
Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization
-
May
-
S. Himavathi, D. Anitha, and A. Muthuramalingam, "Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization," IEEE Transactions on neural networks, Vol. 18, NO.3, May 2007, pp: 880-888.
-
(2007)
IEEE Transactions on Neural Networks
, vol.18
, Issue.3
, pp. 880-888
-
-
Himavathi, S.1
Anitha, D.2
Muthuramalingam, A.3
-
4
-
-
0036989370
-
Neural network implementation on a FPGA
-
Y. J. Chen and D. Plessis, "Neural network implementation on a FPGA," in Proc. IEEE Africon Conf., 2002, vol. 1, pp. 337-342.
-
Proc. IEEE Africon Conf., 2002
, vol.1
, pp. 337-342
-
-
Chen, Y.J.1
Plessis, D.2
-
5
-
-
0027206090
-
Fast neural networks without multipliers
-
Jan
-
M. Marchesi, G. Orlandi, F. Piazza, and A. Uncini, "Fast neural networks without multipliers," IEEE Trans. Neural Netw., vol. 4, no. 1, Jan. 1993, pp.53-62.
-
(1993)
IEEE Trans. Neural Netw.
, vol.4
, Issue.1
, pp. 53-62
-
-
Marchesi, M.1
Orlandi, G.2
Piazza, F.3
Uncini, A.4
-
6
-
-
0033322982
-
Towards an FPGA based reconfigurable computing environment for neural network implementations
-
Sep
-
J. Zhu, G. J. Milne, and B. K. Gunther, "Towards an FPGA based reconfigurable computing environment for neural network implementations," Inst. Elect. Eng. Proc. Artif. Neural Netw., vol. 2, no. 470,Sep. 1999,pp. 661-666.
-
(1999)
Inst. Elect. Eng. Proc. Artif. Neural Netw.
, vol.2
, Issue.470
, pp. 661-666
-
-
Zhu, J.1
Milne, G.J.2
Gunther, B.K.3
-
7
-
-
6344229354
-
Highly efficient limited range multipliers for LUT-based FPGA architectures
-
Oct
-
R. H. Turner and R. F. Woods, "Highly efficient limited range multipliers for LUT-based FPGA architectures," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 10, Oct. 2004, pp. 1113-1117.
-
(2004)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.15
, Issue.10
, pp. 1113-1117
-
-
Turner, R.H.1
Woods, R.F.2
-
8
-
-
0034789767
-
A new neural network approach to induction motor speed control
-
M. Cristea and A. Dinu, "A new neural network approach to induction motor speed control," in Proc. IEEE Power Electron. Specialist Conf., 2001, vol. 2, pp. 784-788.
-
Proc. IEEE Power Electron. Specialist Conf., 2001
, vol.2
, pp. 784-788
-
-
Cristea, M.1
Dinu, A.2
-
10
-
-
0032265783
-
FPGA implementation of a multilayer preceptron neural network using VHDL
-
Y. Taright and M. Hubin, "FPGA implementation of a multilayer preceptron neural network using VHDL," Proc. Int. Conf. Signal Process. (ICSP), vol. 2, 1998, pp. 1306-1310.
-
(1998)
Proc. Int. Conf. Signal Process. (ICSP)
, vol.2
, pp. 1306-1310
-
-
Taright, Y.1
Hubin, M.2
-
11
-
-
34248672477
-
Hardware implementation of neural network on FPGA for accidents diagnosis of the multi-purpose reactor of Egypt
-
Dec.
-
M. M. Syiam, H. M. Klash, I. I. Mahmoud, and S. S. Haggag, "Hardware implementation of neural network on FPGA for accidents diagnosis of the multi-purpose reactor of Egypt," in Proc. 15th Int. Conf. Microelectron. (ICM), Dec. 2003, pp. 326-329.
-
(2003)
Proc. 15th Int. Conf. Microelectron. (ICM)
, pp. 326-329
-
-
Syiam, M.M.1
Klash, H.M.2
Mahmoud, I.I.3
Haggag, S.S.4
-
13
-
-
0026838206
-
GANGLION- A Fast Field- Programmable Gate Array Implementation of a Connectionist Classifier
-
C.E. Cox, W.E. Blanz, "GANGLION- A Fast Field- Programmable Gate Array Implementation of a Connectionist Classifier", Journal of Solid State Circuits, 1992, 27 (3): 288-299.
-
(1992)
Journal of Solid State Circuits
, vol.27
, Issue.3
, pp. 288-299
-
-
Cox, C.E.1
Blanz, W.E.2
-
14
-
-
0030104367
-
Programmable Active Memories: Reconfigurable Systems Come of Age
-
V. Jean, B. Patrice, R. Didier, S. Mark, T. Hervé, B. Philippe. "Programmable Active Memories: Reconfigurable Systems Come of Age", IEEE Transactions on VLSI Systems, 1996, 4(1): 56-69.
-
(1996)
IEEE Transactions on VLSI Systems
, vol.4
, Issue.1
, pp. 56-69
-
-
Jean, V.1
Patrice, B.2
Didier, R.3
Mark, S.4
Hervé, T.5
Philippe, B.6
-
15
-
-
33750201788
-
Hardware implementation of multilayer feed forward network with intelligent neuron
-
Z Haiyan, L Xin, Hardware implementation of multilayer feed forward network with intelligent neuron, Journal of Harbin Engineering University, 2006, 27: 40-45.
-
(2006)
Journal of Harbin Engineering University
, vol.27
, pp. 40-45
-
-
Haiyan, Z.1
Xin, L.2
-
16
-
-
63349102619
-
Dynamic coprocessor management for FPGA-enhanced compute platforms
-
ACM
-
C. Huang, F. Vahid, "Dynamic coprocessor management for FPGA-enhanced compute platforms", Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, ACM, 2008, Pages 71-78
-
(2008)
Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
, pp. 71-78
-
-
Huang, C.1
Vahid, F.2
-
17
-
-
50249100836
-
-
San Fransisco, CA: Morgan Kaufmann, November 02
-
Scott Hauck, Andre Dehon, " Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", San Fransisco, CA: Morgan Kaufmann, November 02,2007.
-
(2007)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
-
-
Hauck, S.1
Dehon, A.2
-
19
-
-
23044500767
-
Study on denoising techniques for ultrasonic signals in wavelet domain based on neural networks
-
Y. Keji, Study on denoising techniques for ultrasonic signals in wavelet domain based on neural networks, Journal of Zhejiang University (Engineering Science), 2005,39 (6): 775-779.
-
(2005)
Journal of Zhejiang University (Engineering Science)
, vol.39
, Issue.6
, pp. 775-779
-
-
Keji, Y.1
-
20
-
-
34248640484
-
Multilayer feedforward neural networks are universal approximators
-
K. M. Hornick, M. Stinchcombe, and H. white, "Multilayer feedforward neural networks are universal approximators," Neural Netw., vol. 2, no. 5, pp. 141-154, 1985.
-
(1985)
Neural Netw
, vol.2
, Issue.5
, pp. 141-154
-
-
Hornick, K.M.1
Stinchcombe, M.2
White, H.3
|