Highly efficient, limited range multipliers for LUT-based FPGA architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 10, 2004, Pages 1113-1117

  Turner, R H ^a   Woods, R F ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Discrete cosine transform (DCT); Multiplier less multiplier blocks; Poly phase filters; Reconfigurable multipliers; Signed digit encoding

Indexed keywords

ALGORITHMS; COSINE TRANSFORMS; DIGITAL SIGNAL PROCESSING; FREQUENCY MULTIPLYING CIRCUITS; LOGIC CIRCUITS; MULTIPLEXING; OPTIMIZATION; SIGNAL ENCODING;

DISCRETE COSINE TRANSFORMS (DCT); REDUCED COEFFICIENT MULTIPLIERS (RCM); SIGNED DIGIT (SD);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 6344229354     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.833399     Document Type: Conference Paper

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