RRANN: a hardware implementation of the backpropagation algorithm using reconfigurable FPGAs

IEEE International Conference on Neural Networks - Conference Proceedings

Volumn 4, Issue , 1994, Pages 2097-2102

  Eldredge, James G ^a   Hutchings, Brad L ^a  

^a BRIGHAM YOUNG UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; ERRORS; LEARNING SYSTEMS; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; PERFORMANCE; RESPONSE TIME (COMPUTER SYSTEMS);

ACTIVATION FUNCTION; BACKPROPAGATION ALGORITHM; FEED FORWARD; FIELD PROGRAMMABLE GATE ARRAYS; RUNTIME RECONFIGURATION ARTIFICIAL NEURAL NETWORKS; SCALABILITY; TIME MULTIPLEXED BUS;

NEURAL NETWORKS;

EID: 0028752759     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)