Minimizing the power consumption of a chip multiprocessor under an average throughput constraint

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 362-371

  Ghasemazar, Mohammad ^a   Pakbaznia, Ehsan ^a   Pedram, Massoud ^a  

^a University of Southern California   (United States)

Author keywords

Chip multiprocessor; Closed loop control; Hierarchical power management; Power minimization

Indexed keywords

AVERAGE POWER; AVERAGE THROUGHPUT; CHIP MULTIPROCESSOR; CHIP MULTIPROCESSORS; CLOSED-LOOP CONTROL; CLOSED-LOOP FEEDBACK CONTROL; CORE LEVELS; GRAIN DYNAMICS; HIERARCHICAL POWER MANAGEMENT; HIGH EFFICACY; MULTI-CORE SYSTEMS; POWER CONSUMPTION; POWER MANAGEMENTS; POWER MINIMIZATION; TASK ASSIGNMENT; TOTAL POWER CONSUMPTION;

ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; OPTIMIZATION;

CLOSED LOOP CONTROL SYSTEMS;

EID: 77952625758     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450550     Document Type: Conference Paper

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