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Volumn 48, Issue 4 PART 2, 2009, Pages

Novel circuitry configuration with paired-cell erase operation for high-density 90-nm embedded resistive random access memory

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; ERASE OPERATION; FEATURE SIZES; HIGH-DENSITY; HIGH-SPEED; MEMORY CELL; MEMORY CELL SIZE; RESISTIVE RANDOM ACCESS MEMORY; WRITE OPERATIONS;

SEMICONDUCTOR STORAGE; SPICE;

RANDOM ACCESS STORAGE;

EID: 77952482837 PISSN: 00214922 EISSN: 13474065 Source Type: Journal
DOI: 10.1143/JJAP.48.04C075 Document Type: Article

Times cited : (7)

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