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Volumn , Issue , 2009, Pages

Feasibility study of 70nm pitch Cu/porous low-k D/D integration featuring EUV lithography toward 22nm generation

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER METALS; CIRCUIT DESIGNS; DUAL DAMASCENE INTERCONNECTS; ELECTROMIGRATION RELIABILITY; EUV LITHOGRAPHY; FEASIBILITY STUDIES; LOW RESISTIVITY; POROUS SILICA; WIRING CAPACITANCE;

EID: 77952342643     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424271     Document Type: Conference Paper
Times cited : (9)

References (8)
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    • Design impact study of wiring size and barrier metal on device performance toward 22nm-node featuring EUV lithography
    • N. Nakamura et al., "Design impact study of wiring size and barrier metal on device performance toward 22nm-node featuring EUV lithography", IEEE IITC, 2.4 (2009) pp 14-16.
    • (2009) IEEE IITC , vol.24 , pp. 14-16
    • Nakamura, N.1
  • 3
    • 50949119154 scopus 로고    scopus 로고
    • Amorphous Ru / polycrystalline Ru highly reliable stacked layer barrier technology
    • 5.6
    • S. Ogawa et al., "Amorphous Ru / polycrystalline Ru highly reliable stacked layer barrier technology", IEEE IITC, 5.6 (2008) pp 102-104.
    • (2008) IEEE IITC , pp. 102-104
    • Ogawa, S.1
  • 4
    • 64549135008 scopus 로고    scopus 로고
    • Comprehensive study of 32 nm node ultralow-k/Cu (keff=2.6) dual damascene integration featuring short TAT silylated Porous Silica (k=2.1)
    • 26.6
    • N. Oda et al, "Comprehensive study of 32 nm node ultralow-k/Cu (keff=2.6) dual damascene integration featuring short TAT silylated Porous Silica (k=2.1)", IEDM Tech. Dig., 26.6 (2008) pp. 615-618.
    • (2008) IEDM Tech. Dig. , pp. 615-618
    • Oda, N.1
  • 5
    • 50149092597 scopus 로고    scopus 로고
    • Selete's EUV program: Progress and challenges
    • I. Mori et al, "Selete's EUV program: progress and challenges", Proc. of SPIE Vol. 6921, 692102-1-12 (2008).
    • (2008) Proc. of SPIE , vol.6921 , pp. 692102-692112
    • Mori, I.1
  • 6
    • 64549095617 scopus 로고    scopus 로고
    • Reduction effect of line edge roughness on time-dependent dielectric breakdown lifetime of Cu/low-k interconnects by using CF3I etching
    • Mar./Apr.
    • E. Soda et al., "Reduction effect of line edge roughness on time-dependent dielectric breakdown lifetime of Cu/low-k interconnects by using CF3I etching", J. Vacuum Science and Technology, B 27(2), Mar./Apr. (2009) pp. 649-653.
    • (2009) J. Vacuum Science and Technology , vol.B 27 , Issue.2 , pp. 649-653
    • Soda, E.1
  • 7
    • 68349120447 scopus 로고    scopus 로고
    • Flare impact and correction for critical dimension control with full-field exposure tool
    • H. Aoyama et al., "Flare impact and correction for critical dimension control with full-field exposure tool" Jpn. J. Appl. Phys., 48 (2009) 056510.
    • (2009) Jpn. J. Appl. Phys. , vol.48 , pp. 056510
    • Aoyama, H.1
  • 8
    • 70349473210 scopus 로고    scopus 로고
    • Packaging characteristics of 6-layer Ultra Low-k/Cu dual damascene interconnect featuring advanced Scalable Porous Silica (k=2.1)
    • S. Chikaki et al., "Packaging characteristics of 6-layer Ultra Low-k/Cu dual damascene interconnect featuring advanced Scalable Porous Silica (k=2.1)", IEEE IITC, 7.10 (2009) pp 110- 112.
    • (2009) IEEE IITC , vol.710 , pp. 110-112
    • Chikaki, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.