Comprehensive study of 32 nm node ultralow-k/Cu (keff=2.6) dual damascene integration featuring short TAT silylated porous silica (k=2.1)

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Oda, N ^a   Chikaki, S ^a   Kubota, T ^a   Nakao, S ^a   Tomioka, K ^a   Soda, E ^a   Nakamura, N ^a   Nogawa, J ^b   Kawashima, Y ^b   Hayashi, R ^b   Saito, S ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

32NM NODES; CIRCUIT UNDER PADS; COMPREHENSIVE STUDIES; DUAL DAMASCENE INTEGRATIONS; DUAL DAMASCENE STRUCTURES; HIGH POROSITIES; INTERCONNECT RELIABILITIES; POROUS SILICAS; SILYLATION; WIRING CAPACITANCES;

ELECTRON DEVICES; NANOTECHNOLOGY; REINFORCEMENT; SILANES; SILICA;

TURNAROUND TIME;

EID: 64549135008     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796766     Document Type: Conference Paper

References (6)

1. M. Tada et al., "Plasma co-polymerization technology with molecular- level structure tightening in "In-situ" SiOCH stacks for 32nm-node Cu interconnects," IEDM Tech. Dig., 13.1 (2006) pp. 351-354.
2. T. Watanabe et al., "Robust BEOL process integration with ultra low-k (k=2.0) dielectric and self-formed MnOx barrier technology for 32nm-node and beyond," Intl. Interconnect Tech. Conf., 10.7 (2008) pp. 208-210.
3. R. Gras et al., "300 mm multi level air gap integration for edge interconnect technologies and specific high performance applications," Intl. Interconnect Tech. Conf., 10.3 (2008) pp. 196-198.
4. S. Chikaki et al., "32 nm node ultralow-k(k=2.1)/Cu damascene Multilevel Interconnect using high-porosity (50 %) high-modulus (9 GPa) self- assembled Porous Silica," IEDM Tech. Dig., 37.1 (2007) pp. 969-972.
5. S. Chikaki et al., "Novel self-hydrophobication and pre-reinforcement of fine pore self-assembled Scalable Porous Silica film for quick Turn-Around-Time Low-k/Cu interconnect process," Advanced Metallization Conf., VI. 3 (2008) in press.
6. N. Oda et al., "Chip-level performance maximization using ASIS (Application-specific interconnect structure) wiring design concept for 45 nm CMOS generation," IEICE Trans. Electronics, E90-C, 4 (2007) pp.848-855.