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Volumn , Issue , 2009, Pages 14-16

Design impact study of wiring size and barrier metal on device performance toward 22 nm-node featuring EUV lithography

Author keywords

[No Author keywords available]

Indexed keywords

13.5 NM; BARRIER FILMS; BARRIER METALS; DESIGN IMPACT; DEVICE PERFORMANCE; EFFECTIVE RESISTIVITY; EUV LITHOGRAPHY; GRAIN SIZE; SPEED DISTRIBUTIONS;

EID: 70349452272     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2009.5090328     Document Type: Conference Paper
Times cited : (6)

References (11)
  • 1
    • 70349450179 scopus 로고    scopus 로고
    • Intl. Tech. Roadmap for Semiconductors (ITRS), 2007.
    • Intl. Tech. Roadmap for Semiconductors (ITRS), 2007.
  • 7
    • 50149092597 scopus 로고    scopus 로고
    • I. Mori et al, Proc. of SPIE Vol. 6921 692102-1 (2008).
    • (2008) Proc. of SPIE , vol.6921 , pp. 692102-692111
    • Mori, I.1
  • 10
    • 70349452570 scopus 로고    scopus 로고
    • J. Van Olmen1 et al., Proc of IITC2007 pp.49-51 (2007)
    • J. Van Olmen1 et al., Proc of IITC2007 pp.49-51 (2007)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.