Second-order multi-bit ΣΔ ADC using a pulse-width modulated DAC and an integrating quantizer

2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009

Volumn , Issue , 2009, Pages 37-40

  Prefasi, Enrique ^a   Pun, Ernesto ^a   Hernández, Luis ^a   Paton, Susan ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL SIMULATION; CHARGE RESIDUE; CIRCUIT LEVELS; CIRCUIT NON-IDEALITIES; CMOS TECHNOLOGY; CONVERSION CYCLES; FIRST ORDER; MULTI-BITS; NOISE-SHAPING; PULSEWIDTHS; QUANTIZERS; SECOND ORDERS; SIGMA-DELTA; SIGNAL BANDWIDTH; SINGLE-BIT; SYSTEM LEVEL DESIGN; SYSTEM-LEVEL PERFORMANCE; WIRELESS COMMUNICATION STANDARDS;

CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; DIGITAL INTEGRATED CIRCUITS; MODULATORS; MULTICARRIER MODULATION; WIRELESS TELECOMMUNICATION SYSTEMS;

INTEGRATION;

EID: 77951443621     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2009.5410951     Document Type: Conference Paper

References (8)

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