-
1
-
-
70450060066
-
Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation
-
Claus, C., Huitl, R., Rausch, J., Stechele, W.: Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. In: Proceedings of FPL 2009, Prague, Czech Republic (2009)
-
Proceedings of FPL 2009, Prague, Czech Republic (2009)
-
-
Claus, C.1
Huitl, R.2
Rausch, J.3
Stechele, W.4
-
2
-
-
85117388823
-
AutoVision - A run-time reconfigurable MPSoC architecture for future driver assistance systems
-
Claus, C., Stechele, W., Herkersdorf, A.: AutoVision - a run-time reconfigurable MPSoC architecture for future driver assistance systems. It-Journal 49(3), 181-187 (2007)
-
(2007)
It-Journal
, vol.49
, Issue.3
, pp. 181-187
-
-
Claus, C.1
Stechele, W.2
Herkersdorf, A.3
-
3
-
-
77951285866
-
-
http://www.mobileye-vision.com
-
-
-
-
4
-
-
33645139298
-
On-road vehicle detection: A review
-
Sun, Z., Bebis, G., Miller, R.: On-road vehicle detection: a review. IEEE Transactions on Pattern Analysis and Machine Intelligence 28(5), 694-711 (2006)
-
(2006)
IEEE Transactions on Pattern Analysis and Machine Intelligence
, vol.28
, Issue.5
, pp. 694-711
-
-
Sun, Z.1
Bebis, G.2
Miller, R.3
-
5
-
-
62249219829
-
An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications
-
November
-
Manet, P., Maufroid, D., Tosi, L., Gailliard, G., Mulertt, O., Ciano, M.D., Legat, J.-D., Aulagnier, D., Gamrat, C., Liberati, R., Barba, V.L., Cuvelier, P., Rousseau, B., Gelineau, P.: An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications. EURASIP Journal on Embedded Systems 2008 (November 2008)
-
(2008)
EURASIP Journal on Embedded Systems 2008
-
-
Manet, P.1
Maufroid, D.2
Tosi, L.3
Gailliard, G.4
Mulertt, O.5
Ciano, M.D.6
Legat, J.-D.7
Aulagnier, D.8
Gamrat, C.9
Liberati, R.10
Barba, V.L.11
Cuvelier, P.12
Rousseau, B.13
Gelineau, P.14
-
6
-
-
54949136567
-
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
-
Shelburne, M., Patterson, C., Athanas, P., Jones, M., Martin, B., Fong, R.: Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip. In: Proceedings of FPL 2008, Heidelberg, Germany, pp. 257-262 (2008)
-
(2008)
Proceedings of FPL 2008, Heidelberg, Germany
, pp. 257-262
-
-
Shelburne, M.1
Patterson, C.2
Athanas, P.3
Jones, M.4
Martin, B.5
Fong, R.6
-
7
-
-
63449087213
-
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
-
Sirisuk, P., et al. (eds.) Springer, Heidelberg
-
Bomel, P., Crenne, J., Ye, L., Diguet, J.-P., Gogniat, G.: Ultra-Fast Downloading of Partial Bitstreams through Ethernet. In: Sirisuk, P., et al. (eds.) ARC 2010. LNCS, vol.5992, pp. 72-83. Springer, Heidelberg (2010)
-
(2010)
ARC 2010. LNCS
, vol.5992
, pp. 72-83
-
-
Bomel, P.1
Crenne, J.2
Ye, L.3
Diguet, J.-P.4
Gogniat, G.5
-
8
-
-
70449922693
-
Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
-
Liu, M., Kuehn, W., Lu, Z., Jantsch, A.: Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration. In: Proceedings of FPL 2009, Prague, Czech Republic (2009)
-
Proceedings of FPL 2009, Prague, Czech Republic (2009)
-
-
Liu, M.1
Kuehn, W.2
Lu, Z.3
Jantsch, A.4
-
9
-
-
70449591807
-
High performance FPGA based optical flow calculation using the census transformation
-
Claus, C., Laika, A., Jia, L., Stechele, W.: High performance FPGA based optical flow calculation using the census transformation. In: Proceedings of IV 2009, Xi'an, China (2009)
-
Proceedings of IV 2009, Xi'an, China (2009)
-
-
Claus, C.1
Laika, A.2
Jia, L.3
Stechele, W.4
-
10
-
-
54949092869
-
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput
-
Claus, C., Zhang, B., Stechele, W., Braun, L., Hübner, M., Becker, J.: A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. In: Proceedings of FPL 2008, Heidelberg, Germany, pp. 535-538 (2008)
-
(2008)
Proceedings of FPL 2008, Heidelberg, Germany
, pp. 535-538
-
-
Claus, C.1
Zhang, B.2
Stechele, W.3
Braun, L.4
Hübner, M.5
Becker, J.6
-
11
-
-
36349012325
-
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs
-
Hübner, M., Braun, L., Becker, J., Claus, C., Stechele, W.: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. In: Proceedings of ISVLSI 2007, Porto Alegre, Brazil, pp. 41-46 (2007)
-
(2007)
Proceedings of ISVLSI 2007, Porto Alegre, Brazil
, pp. 41-46
-
-
Hübner, M.1
Braun, L.2
Becker, J.3
Claus, C.4
Stechele, W.5
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