Physical configuration on-line visualization of Xilinx Virtex-II FPGAs

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 41-46

  Hübner, Michael ^a   Braun, Lars ^a   Becker, Jürgen ^a   Claus, Christopher ^b   Stechele, Walter ^b  

^a UNIVERSITY OF KARLSRUHE   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

Dynamic reconfiguration; FPGA; On line visualization

Indexed keywords

DYNAMIC RECONFIGURATION; INTEGRATED RECONFIGURABLE SYSTEMS; ON-LINE VISUALIZATION;

ADAPTIVE SYSTEMS; COMPUTATION THEORY; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; REQUIREMENTS ENGINEERING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 36349012325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.83     Document Type: Conference Paper

References (12)

1. Virtex-II Platform FPGA User Guide, UG002 (v2.0) 23 March 2005
2. Virtex-II Pro and Virtex-II Pro X FPGA User Guide, UG012 (v4.0) 23 March 2005
3. Reiner Hartenstein: "Reconfigurable Technologies", Seminar at Department of Informatics, Kyushu University, Higashi-ku, Fukuoka City, Kyushu, Japan; July 23, 2004
4. Ullmann, B. Grimm, M. Huebner, J. Becker: "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration", RAW04, Santa Fe, USA
5. C. Palma, A. Vieira de Melo, F. G. Moraes, N. Calazans, "Core Communication Interface for FPGAs", Proceedings of 15th Symposium on Integrated Circuits and Systems Design (SBCCI), 2002,Porto Alegre BRAZIL, Page(s): 183-188
6. M. Hübner, C. Schuck, M. Kühnle, J. Becker: "New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-Time Adaptive Microelectronic Circuits", ISVLSI2006, Karlsruhe, Germany
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9. M. Huebner, M. Ullmann, L. Braun, A. Klausmann, J. Becker: "Scalable Application-dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems", FPL 2004, Antwerp, Belgium
10. K. Paulsson, M.Hübner, M. Jung, J. Becker: "Methods for Run-Time Failure Recognition and Recovery in Dynamic and Partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs ", ISVLSI2006, Karlsruhe, Germany
11. K. Paulsson, M. Hübner, J. Becker: "On-Line Optimization of FPGA Power-Dissipation by Exploiting Run-time Adaption of Communication Primitives", SBCCI2006, Brazil
12. B. Blodget, S. McMillan: "A lightweight approach for embedded reconfiguration of FPGAs", Date03, Munich Germany