Minimizing clock latency range in robust clock tree synthesis

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2010, Pages 389-394

  Liu, Wen Hao ^a   Li, Yih Lang ^a   Chen, Hui Chi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; BUFFER INSERTION; CLOCK NETWORK SYNTHESIS; CLOCK SKEWS; CLOCK TREE; CLOCK TREE SYNTHESIS; DELAY VARIATION; MULTIPLE SUPPLY VOLTAGES; WIRE SIZING;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; OPTIMIZATION; TIME DELAY; WIRE;

ELECTRIC CLOCKS;

EID: 77951235487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419849     Document Type: Conference Paper

References (11)

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