Statistical-aware designs for the nm era

2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Volumn , Issue , 2009, Pages 207-210

  Joshi, Rajiv ^a   Kanj, Rouwaida ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

DFM; SRAM; Test; Variation tolerant designs; Yield

Indexed keywords

BIT LINES; CLAMPING METHOD; DESIGN METHODOLOGY; DESIGN SPACES; DFM; DUAL SUPPLY; DYNAMIC NOISE; DYNAMIC STABILITY; MEMORY DESIGN; PROCESS VARIATION; RANDOM VARIATION; SIGNIFICANT IMPACTS;

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

DESIGN;

EID: 77950326755     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2009.5166297     Document Type: Conference Paper

References (14)

1. Y. Nakagome, M Horiguchi, T. Kawahara and K. Itoh, "Review and future prospects of low voltage RAM circuits," IBM Journal of Research and Development, vol. 47, No.5/6, 2003
2. R. V. Joshi et al., "Variability analysis for Sub-100 nm PD/SOI CMOS SRAM cell", Proc. of the 30th ESSCC, 2004, pp. 211-214.
3. K. Zhang et al., "A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply", ISSCC Dig. Tech. Papers, Feb 2005, pp.474-475
4. W. Henkels et al. Us Patent No. 6279144, Aug 21, 2001.
5. L. Chang et al., "Stable SRAM cell design for the 32 nm node and beyond", IEEE Symposium on VLSI Technology, 2005.
6. R. Joshi, "Random Access Memory with stability enhancement and early read elimination", US patent # 7193904, 2007.
7. R. Kanj, R. Joshi, and S. Nassif, "Mixture Importance Sampling and Its Application to the Analysis of SRAM Designs in the Presence of Rare Failure Events", to appear in DAC '06
8. R. Joshi et al., "Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell", ESSDERC 2006.
9. J. Davis et al., "A 5.6GHz 64kB Dual-Read Data Cache for the POWER6™ Processor", ISSCC, pp. 33-34, 2006.
10. Y. Chen, R. Joshi, and D. Plass, "Integrated circuit chip with improved array stability", US Patent # 7,403,412 2005/0063232 A1.
11. L. Hsu, R. V. Joshi, and R. Wong "SRAM with improved noise sensitivity.", US Patent # 6654277.
12. R. Joshi et al., "High Performance 2.4 Mb L1 and L2 Cache Compatible 45nm SRAMs with Yield Improvement Capabilities", VLSI Symposium '08.
13. S. Narasimha et al., "High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography", IEDM 2006
14. R. Joshi et al., "6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM", Proc. VLSI Circuit Symp., pp.28-30, June 2007.