Exploiting memory customization in FPGA for 3D stencil computations

Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Volumn , Issue , 2009, Pages 38-45

  Shafiq, Muhammad ^a,b   Pericàs, Miquel ^a   De La Cruz, Raul ^a   Araya Polo, Mauricio ^a   Navarro, Nacho ^b   Ayguadé, Eduard ^a,b  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DATA DELIVERY; DATA REUSE; DESIGN APPROACHES; FPGA ARCHITECTURES; FPGA DEVICES; INPUT DATAS; LARGE DATA; MEMORY ORGANIZATIONS; MULTI RATE; SCIENTIFIC AND ENGINEERING APPLICATIONS; STENCIL COMPUTATIONS; WORK FOCUS;

ARCHITECTURAL DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

THREE DIMENSIONAL;

EID: 77949404004     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2009.5377644     Document Type: Conference Paper

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