Analysis and design of fully integrated high-power parallel-circuit class-E CMOS power amplifiers

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 3, 2010, Pages 725-734

  Lee, Ockgoo ^a   An, Kyu Hwan ^a   Kim, Hyungwook ^a   Lee, Dong Ho ^a   Han, Jeonghu ^a   Yang, Ki Seok ^b   Lee, Chang Ho ^b   Kim, Haksun ^b   Laskar, Joy ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Samsung Design Center   (United States)

Author keywords

Breakdown; CMOS power amplifier (PA); Parallel combining; Parallel circuit class E PA; Power loss; Transformer

Indexed keywords

CMOS INTEGRATED CIRCUITS; DC TRANSFORMERS; INTEGRATED CIRCUIT DESIGN; TIMING CIRCUITS;

BREAKDOWN; CLASS E; CMOS POWER AMPLIFIERS; PARALLEL COMBINING; POWER-LOSSES; TRANSFORMER;

POWER AMPLIFIERS;

EID: 77949384383     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2023944     Document Type: Article

References (31)

1. K.-C. Tsai and P. R. Gray, "A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications," IEEE J. Solid-State Circuits, vol.34, no.7, pp. 962-970, Jul. 1999.
2. C. Yoo and Q. Huang, "A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25--m CMOS," IEEE J. Solid-State Circuits, vol.36, no.5, pp. 823-830, May 2001.
3. K. L. R. Mertens and M. S. J. Steyaert, "A 700-MHz 1-W fully differential CMOS class-E power amplifier," IEEE J. Solid-State Circuits, vol.37, no.2, pp. 137-141, Feb. 2002.
4. R. Brama, L. Larcher, A. Mazzanti, and F. Svelto, "A 30.5 dBm 48% PAE CMOS class-E PA with integrated balun for RF applications," IEEE J. Solid-State Circuits, vol.43, no.8, pp. 1755-1762, Aug. 2008.
5. N. O. Sokal and A. D. Sokal, "Class E-A new class of high-efficiency tuned single-ended switching power amplifiers," IEEE J. Solid-State Circuits, vol.SSC-10, no.3, pp. 168-176, Jun. 1975.
6. F. Raab, "Idealized operation of the class E tuned power amplifier," IEEE Trans. Circuits Syst., vol.CAS-24, no.12, pp. 725-735, Dec. 1977.
7. I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, "Fully integrated CMOS power amplifier design using the distributed active-transformer architecture," IEEE J. Solid-State Circuits, vol.37, no.3, pp. 371-383, Mar. 2002.
8. C. Park, D. H. Lee, J. Han, and S. Hong, "Tournament-shaped magnetically coupled power-combiner architecture for RF CMOS power amplifier," IEEE Trans. Microw. Theory Tech., vol.55, no.10, pp. 2034-2042, Oct. 2007.
9. K. H. An, O. Lee, H. Kim, D. H. Lee, J. Han, K. S. Yang, Y. Kim, J. J. Chang, W.Woo, C.-H. Lee, H. Kim, and J. Laskar, "Power-combining transformer techniques for fully-integrated CMOS power amplifiers," IEEE J. Solid-State Circuits, vol.43, no.5, pp. 1064-1075, May 2008.
10. D. H. Lee, C. Park, J. Han, Y. Kim, S. Hong, C.-H. Lee, and J. Laskar, "A load-shared CMOS power amplifier with efficiency boosting at low power mode for polar transmitters," IEEE Trans. Microw. Theory Tech., vol.56, no.7, pp. 1565-1574, Jul. 2008.
11. N. O. Sokal, "Class E-RF power amplifiers," QEX, no.204, pp. 9-20, 2001.
12. D. J. Kessler and M. K. Kazimierczuk, "Power losses and efficiency of class-E power amplifier at any duty ratio," IEEE Trans. Circuits Syst., vol.51, no.9, pp. 1675-1689, Sep. 2004.
13. R. E. Zulinski and J. W. Steadman, "Class E power amplifiers and frequency multipliers with finite DC-feed inductance," IEEE Trans. Circuits Syst., vol.CAS-34, no.9, pp. 1074-1087, Sep. 1987.
14. C. P. Avratoglou, N. C. Voulgaris, and F. I. Ioannidou, "Analysis and design of a generalized class E tuned power amplifier," IEEE Trans. Circuits Syst., vol.36, no.8, pp. 1068-1079, Aug. 1989.
15. G. H. Smith and R. E. Zulinski, "An exact analysis of class E amplifiers with finite DC-feed inductance at any output Q," IEEE Trans. Circuits Syst., vol.37, no.4, pp. 530-534, Apr. 1990.
16. T. Mury and V. F. Fusco, "Analysis of the effect of finite DC blocking capacitance and finite DC feed inductance on the performance of inverse class-E amplifiers," Proc. Inst. Electr. Eng.-Circuits, Devices Syst., vol.153, pp. 129-135, Apr. 2006.
17. M. Acar, A. J. Annema, and B. Nauta, "Analytical design equations for class-E power amplifiers," IEEE Trans. Circuits Syst., vol.54, no.12, pp. 2706-2717, Dec. 2007.
18. A. V. Grebennikov and H. Jaeger, "Class E with parallel circuit-A new challenge for high-efficiency RF and microwave power amplifiers," in IEEE MTT-S Int. Microw. Symp. Dig., 2002, pp. 1627-1630.
19. N. Kumar, C. Prakash, A. Grebennikov, and A. Mediano, "High-efficiency broadband parallel-circuit class E RF power amplifier with reactance- compensation technique," IEEE Trans. Microw. Theory Tech., vol.56, no.3, pp. 604-612, Mar. 2008.
20. A. Grebennikov and N. O. Sokal, Switchmode RF Power Amplifiers. Newton, MA: Newnes, 2007.
21. F. H. Raab and N. O. Sokal, "Transistor power losses in the class E tuned power amplifier," IEEE J. Solid-State Circuits, vol.SSC-13, no.6, pp. 912-914, Dec. 1978.
22. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2004.
23. P. Reynaert and M. S. J. Seyaert, "A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2598-2608, Mar. 2005.
24. A. Shirvani, D. K. Su, and B. A.Wooley, "ACMOSRF power amplifier with parallel amplification for efficient power control," IEEE J. Solid- State Circuits, vol.37, no.6, pp. 684-693, Jun. 2002.
25. P. Reynaert and M. S. J. Seyaert, "A 2.45-GHz 0.13--m CMOS PA with parallel amplification," IEEE J. Solid-State Circuits, vol.42, no.3, pp. 551-562, Mar. 2007.
26. I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, "Distributed active transformer-A new power-combining and impedance-transformation technique," IEEE Trans. Microw. Theory Tech., vol.50, no.1, pp. 316-331, Jan. 2002.
27. O. Lee, K. S. Yang, K. H. An, Y. Kim, H. Kim, J. J. Chang, W. Woo, C.-H. Lee, and J. Laskar, "A 1.8-GHz 2-watt fully integrated CMOS push-pull parallel-combined power amplifier design," in Proc. IEEE RFIC Symp., 2007, pp. 435-438.
28. K. H. An, Y. Kim, O. Lee, K. S. Yang, H. Kim, J. J. Chang, W. Woo, C.-H. Lee, and J. Laskar, "A monolithic voltage-boosting parallel-primary transformer structures for fully integrated CMOSpower amplifier design," in Proc. IEEE RFIC Symp., 2007, pp. 419-422.
29. P. Haldi, D. Chowdhury, P. Reynaert, L. Gang, and A. M. Niknejad, "A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS," IEEE J. Solid-State Circuits, vol.43, no.5, pp. 1054-1063, May 2008.
30. J. R. Long, "Monolithic transformers for silicon RF IC design," IEEE J. Solid-State Circuits, vol.35, no.9, pp. 1368-1382, Sep. 2000.
31. A. Mazzanti, L. Larcher, R. Brama, and F. Svelto, "Analysis of reliability and power efficiency in cascode class-E PAs," IEEE J. Solid-State Circuits, vol.41, no.5, pp. 1222-1229, May 2006.