Power-combining transformer techniques for fully-integrated CMOS power amplifiers

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 5, 2008, Pages 1064-1074

  An, Kyu Hwan ^a,b   Lee, Ockgoo ^a,b   Kim, Hyungwook ^a,b   Lee, Dong Ho ^a,b   Han, Jeonghu ^a,b   Yang, Ki Seok ^a,c   Kim, Younsuk ^a,d   Chang, Jae Joon ^a,c   Woo, Wangmyong ^a,c   Lee, Chang Ho ^a,c   Kim, Haksun ^a,e   Laskar, Joy ^a,b  

^a IEEE

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c Samsung Design Center   (United States)

^d Samsung Electro Mechanics   (South Korea)

^e Hanbat National University   (South Korea)

Author keywords

CMOS integrated circuits; Impedance matching; Power amplifiers; Transformers

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC UTILITIES; IMPEDANCE MATCHING (ELECTRIC); POWER AMPLIFIERS;

PARALLEL COMBINING TRANSFORMERS; PARASITIC RESISTANCE;

POWER TRANSFORMERS;

EID: 42649109036     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.920349     Document Type: Conference Paper

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