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Volumn , Issue , 2009, Pages 479-482

The effect of node size, heterogeneity, and network size on FPGA based NoCs

Author keywords

[No Author keywords available]

Indexed keywords

APPROPRIATE TOPOLOGY; COMPLEX SYSTEMS; COMPUTING NODES; CRITICAL PATHS; ELECTRICAL CHARACTERISTIC; MULTIPROCESSOR NETWORKS; NETWORK NODE; NETWORK SIZE; NETWORKS ON CHIPS; POINT-TO-POINT LINK;

EID: 77949357507     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2009.5377628     Document Type: Conference Paper
Times cited : (9)

References (13)
  • 1
    • 0004093751 scopus 로고    scopus 로고
    • NY, Online, Available
    • IBM Corporation, NY, "The Coreconnect Bus Architecture," (1999). [Online]. Available: http://chips.ibm.com
    • (1999) The Coreconnect Bus Architecture
  • 2
    • 77949368779 scopus 로고    scopus 로고
    • OpenCores.org, The WISHBONE system architecture, (2002). [Online]. Available: http://opencores.org/projects.cgi/web/wishbone
    • OpenCores.org, "The WISHBONE system architecture," (2002). [Online]. Available: http://opencores.org/projects.cgi/web/wishbone
  • 5
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. 38th Conf. Des. Autom. (DAC), 2001, pp. 684-689.
    • (2001) Proc. 38th Conf. Des. Autom. (DAC) , pp. 684-689
    • Dally, W.J.1    Towles, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.