Hardwired networks on chip in FPGAs to unify functional and configuration interconnects

Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Volumn , Issue , 2008, Pages 45-54

  Goossens, Kees ^a,b   Bennebroek, Martijn ^c   Hur, Jae Young ^b   Wahlah, Muhammad Aqeel ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURATION INTERCONNECTS; NETWORKS ON CHIP (NOC); ONLINE VERIFICATION;

COMPUTER PROGRAMMING; INTERCONNECTION NETWORKS; INTERNET PROTOCOLS; VERIFICATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 44149102221     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2008.4492724     Document Type: Conference Paper

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