Variation-aware scheduling for chip multiprocessors with thread level redundancy

2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2009

Volumn , Issue , 2009, Pages 17-22

  Dong, Jianbo ^a,b   Zhang, Lei ^a   Han, Yinhe ^a,b   Yan, Guihai ^a,b   Li, Xiaowei ^a,b  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

Author keywords

Chip multiprocessor; Process variation; Scheduling; Thread level redundancy

Indexed keywords

0-1 PROGRAMMING PROBLEM; APPLICATION SCHEDULING; CHIP MULTIPROCESSOR; EFFICIENT SCHEDULING; IN-CHIP; PROCESS VARIATION; SOFT-ERROR TOLERANCE;

MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; QUALITY ASSURANCE; REDUNDANCY; SYSTEMS ANALYSIS;

SCHEDULING ALGORITHMS;

EID: 77649299403     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2009.12     Document Type: Conference Paper

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