Patterning and templating for nanoelectronics

Advanced Materials

Volumn 22, Issue 6, 2010, Pages 769-778

  Galatsis, Kosmas ^a,b   Wang, Kang L ^b   Ozkan, Mihri ^c   Ozkan, Cengiz S ^c   Huang, Yu ^b   Chang, Jane P ^b   Monbouquette, Harold G ^b   Chen, Yong ^a   Nealey, Paul ^d   Botros, Youssry ^e  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Engineering IV   (United States)

^c University of California Riverside   (United States)

^d UNIVERSITY OF WISCONSIN MADISON   (United States)

^e INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALTERNATIVE APPROACH; CMOS SCALING; INFORMATION PROCESSING; LOS ANGELES; MAGNETIC DOTS; MOORE'S LAW; NANOARCHITECTURES; PATTERNING METHODS; PATTERNING TECHNIQUES; PATTERNING TECHNOLOGY; SEMICONDUCTOR INDUSTRY; SILICON INTEGRATED CIRCUITS; TECHNOLOGY NODES; TEMPLATING; TOPDOWN;

DATA PROCESSING; LITHOGRAPHY; SEMICONDUCTOR DEVICE MANUFACTURE;

NANOELECTRONICS;

DNA; NANOMATERIAL; QUANTUM DOT;

ARTICLE; CHEMISTRY; ELECTRONICS; SEMICONDUCTOR;

DNA; ELECTRONICS; NANOSTRUCTURES; QUANTUM DOTS; SEMICONDUCTORS;

EID: 77049107410     PISSN: 09359648     EISSN: 15214095     Source Type: Journal    
DOI: 10.1002/adma.200901689     Document Type: Article

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