Patterned ZnO nanorods network transistor fabricated by low-temperature hydrothermal process

Microelectronic Engineering

Volumn 87, Issue 5-8, 2010, Pages 1483-1486

  Chen, Tao ^a   Liu, Shu Yi ^a   Xie, Qi ^a   Jiang, Yu Long ^a   Ru, Guo Ping ^a   Liu, Ran ^a   Qu, Xin Ping ^a  

^a ASIC and System   (China)

Author keywords

Field effect transistor; Nanorods; Network structure; ZnO

Indexed keywords

CHANNEL REGION; DEPLETION MODES; FABRICATION TEMPERATURE; FIELD-EFFECT MOBILITIES; GATE STRUCTURE; HYDROTHERMAL PROCESS; LIFT-OFF PROCESS; LOW TEMPERATURES; NETWORK STRUCTURES; NETWORK TRANSISTORS; SEED LAYER; SOL-GEL METHODS; SOURCE-DRAIN ELECTRODES; TRANSPARENT SUBSTRATE; WHOLE PROCESS; ZNO; ZNO NANOROD;

FABRICATION; FIELD EFFECT TRANSISTORS; NANORODS; SOL-GEL PROCESS;

ZINC OXIDE;

EID: 76949095163     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.11.077     Document Type: Article

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