The use of Mahalanobis-Taguchi System to improve flip-chip bumping height inspection efficiency

Microelectronics Reliability

Volumn 50, Issue 3, 2010, Pages 407-414

  Yang, Taho ^a   Cheng, Yuan Ting ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CLASSIFICATION ACCURACY; FLIP CHIP; FLIP-CHIP BUMPING; FLIP-CHIP PACKAGING; HEIGHT MEASUREMENT; HIGH-ACCURACY; INSPECTION EFFICIENCY; INSPECTION FEATURES; INSPECTION PROCESS; INSPECTION TIME; MAHALANOBIS-TAGUCHI SYSTEMS; OPERATION TIME; WIRE BONDING;

CHIP SCALE PACKAGES; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; INFORMATION DISSEMINATION; MICROELECTRONICS;

INSPECTION;

EID: 76849111465     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2009.12.001     Document Type: Article

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