The era of many-modules SoC: Revisiting the NoC mapping problem

2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42

Volumn , Issue , 2009, Pages 43-48

  Walter, Isask'har ^a   Cidon, Israel ^a   Kolodny, Avinoam ^a   Sigalov, Daniel ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Mapping; Network on chip; Optimization; System on chip

Indexed keywords

APPLICATION DATA; DESIGN COSTS; FUNCTIONAL UNITS; INHERENT PARALLELISM; MAPPING ALGORITHMS; MAPPING PROBLEM; MULTI CORE; ON CHIPS; OPTIMIZATION SYSTEM; POWER CONSUMED; SPECIALIZED HARDWARE; SYSTEM ON-CHIP; TECHNOLOGY SCALING; TIMING REQUIREMENTS;

CONFORMAL MAPPING; PROGRAMMABLE LOGIC CONTROLLERS;

MICROPROCESSOR CHIPS;

EID: 76749159917     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1645213.1645224     Document Type: Conference Paper

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