A 2D analytical model for SCEs in MOSFETs with high-k gate dielectric

Semiconductor Science and Technology

Volumn 25, Issue 3, 2010, Pages

  Xie, Qian ^a   Xu, Jun ^a   Ren, Tianling ^a   Taur, Yuan ^b  

^a TSINGHUA NATIONAL LABORATORY FOR INFORMATION SCIENCE AND TECHNOLOGY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

2-D NUMERICAL SIMULATION; 2D POISSON; ANALYTICAL MODEL; CHANNEL LENGTH; COMPACT MODELING; DRAIN-INDUCED BARRIER LOWERING; EXPLICIT EXPRESSIONS; FITTING PARAMETERS; HIGH-K GATE DIELECTRICS; INVERSE SLOPE; KEY FEATURE; MINIMUM SURFACES; MOS-FET; MOSFETS; POTENTIAL MODEL; SHORT-CHANNEL EFFECT; SUB-THRESHOLD CURRENT;

DIELECTRIC DEVICES; GATES (TRANSISTOR); GENE EXPRESSION; MODELS; MOSFET DEVICES; POISSON EQUATION; TWO DIMENSIONAL;

GATE DIELECTRICS;

EID: 76649117149     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/25/3/035012     Document Type: Article

References (11)

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