Global routing revisited

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 805-808

  Moffitt, Michael D ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC PRINCIPLES; GLOBAL ROUTING; PHYSICAL SYNTHESIS; RECENT PROGRESS; RESEARCH COMMUNITIES; ROUTING PROBLEMS; STATE OF THE ART;

COMPUTER AIDED DESIGN;

EID: 76349088967     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687549     Document Type: Conference Paper

References (29)

1. C. Albrecht. Global routing by new approximation algorithms for multicommodity flow. IEEE Trans. on CAD of Integrated Circuits and Systems, 20(5):622-632, 2001.
2. C. J. Alpert, C. Chu, and P. G. Villarrubia. The coming of age of physical synthesis. In Proceedings of the 2007 International Conference on Computer-Aided Design, 2007.
3. Y.-J. Chang, Y.-T. Lee, and T.-C. Wang. NTHU-Route 2.0: a fast and stable global router. In Proceedings of the 2008 International Conference on Computer-Aided Design (ICCAD 2008), pages 338-343, 2008.
4. H.-Y. Chen, C.-H. Hsu, and Y.-W. Chang. High-performance global routing with fast overflow reduction. In Proceedings of the 14th Asia South Pacific Design Automation Conference (ASP-DAC 2009), pages 582-587, 2009.
5. M. Cho, K. Lu, K. Yuan, and D. Z. Pan. BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability. ACM Trans. Design Autom. Electr. Syst., 14(2), 2009.
6. C. Chu and Y.-C.Wong. FLUTE: Fast lookup table based rectilinear steiner minimal tree algorithm for VLSI design. IEEE Trans. on CAD of Integrated Circuits and Systems, 2007.
7. D. W. Hightower. A solution to line routing problems on the continuous plane. In The Sixth Design Automation Workshop, pages 1-24, 1969.
8. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang. Multi-layer global routing considering via and wire capacities. In Proceedings of the 2008 International Conference on Computer-Aided Design (ICCAD 2008), pages 350-355, 2008.
9. J. Hu and S. S. Sapatnekar. A survey on multi-net global routing for integrated circuits. Integration, the VLSI Journal, 31(1):1-49, 2001.
10. J. Hu and S. S. Sapatnekar. A timing-constrained simultaneous global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems, 21(9):1025-1036, 2002.
11. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh. Pattern routing: use and theory for increasing predictability and avoiding coupling. IEEE Trans. on CAD of Integrated Circuits and Systems, 21(7):777-790, 2002.
12. M. A. Kazda, P. M. Kotecha, A. P. Matheny, L. Reddy, L. H. Trevillyan, and P. G. Villarrubia. US patent application 20080209376: System and method for sign-off timing closure of a VLSI chip, 2008.
13. C. Y. Lee. An algorithm for path connection and its applications. IRE Transactions on Electronic Computers, EC-10(3):346-365, 1961.
14. T.-H. Lee and T.-C. Wang. Congestion-constrained layer assignment for via minimization in global routing. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(9):1643-1656, 2008.
15. Z. Li, C. J. Alpert, S. Hu, T. Muhmud, S. T. Quay, and P. G. Villarrubia. Fast interconnect synthesis with layer assignment. In Proceedings of the 2008 International Symposium on Physical Design (ISPD 2008), pages 71-77, 2008.
16. L. McMurchie and C. Ebeling. PathFinder: A negotiationbased performance-driven router for FPGAs. In Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, pages 111-117, 1995.
17. M. D. Moffitt. MaizeRouter: Engineering an effective global router. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(11):2017-2026, 2008.
18. M. D. Moffitt, J. A. Roy, and I. L. Markov. The coming of age of (academic) global routing. In Proceedings of the 2008 International Symposium on Physical Design (ISPD 2008), pages 148-155, 2008.
19. E. F. Moore. Shortest path through a maze. Annals of Computation Laboratory, pages 285-292, 1959.
20. G.-J. Nam, C. C. N. Sze, and M. C. Yildiz. The ISPD global routing benchmark suite. In Proceedings of the 2008 International Symposium on Physical Design, pages 156-159, 2008.
21. G.-J. Nam, M. C. Yildiz, D. Z. Pan, and P. H. Madden. ISPD placement contest updates and ISPD 2007 global routing contest. In Proceedings of the 2007 International Symposium on Physical Design (ISPD 2007), page 167, 2007.
22. M. M. Ozdal and M. D. F. Wong. Archer: A history-based global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems, 28(4):528-540, 2009.
23. P. Raghavan and C. D. Thompson. Multiterminal global routing: a deterministic approximation scheme. Algorithmica, 6:73-82, 1991.
24. J. A. Roy and I. L. Markov. High-performance routing at the nanometer scale. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(6):1066-1077, 2008.
25. L. Scheffer, L. Lavagno, and G. Martin. EDA for IC Implementation, Circuit Design, and Process Technology. CRC, 2006.
26. E. Shragowitz and S. Keel. A global router based on a multicommodity flow model. Integration: the VLSI Journal, 5(1):3-16, 1987.
27. W. Swartz. Issues in global routing. In Proceedings of the 2008 International Symposium on Physical Design (ISPD 2008), pages 142-147, 2008.
28. J. T. L. Tai-Hsuan Wu, Azadeh Davoodi. GRIP: Scalable 3D global routing using integer programming. In Proceedings of the 46th Design Automation Conference (DAC 2009), pages 320-325, 2009.
29. Y. Xu, Y. Zhang, and C. Chu. FastRoute 4.0: global router with efficient via minimization. In Proceedings of the 14th Asia South Pacific Design Automation Conference (ASP-DAC 2009), pages 576-581, 2009.