Congestion-constrained layer assignment for via minimization in global routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 9, 2008, Pages 1643-1656

  Lee, Tsung Hsien ^a   Wang, Ting Chi ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Global routing; Layer assignment; Physical design; Via minimization

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER NETWORKS; MATHEMATICAL PROGRAMMING; MULTILAYERS; SYSTEMS ENGINEERING;

GLOBAL ROUTING; LAYER ASSIGNMENT; PHYSICAL DESIGN; VIA MINIMIZATION;

ROUTING ALGORITHMS;

EID: 50549090491     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.927733     Document Type: Article

References (23)

1. R. Kastner, E. Bozogzadeh, and M. Sarrafzadeh, "Predictable routing," in Proc. Int. Conf. Comput.-Aided Des., 2000, pp. 110-113.
2. M. Pan and C. Chu, "FastRoute: A step to integrate global routing into placement," in Proc. Int. Conf. Comput.-Aided Des., 2006, pp. 464-471.
3. M. Pan and C. Chu, "FastRoute 2.0: A high-quality and efficient global router," in Proc. Asia South Pacific. Des. Autom. Conf., 2007, pp. 250-255.
4. M. Cho and D. Z. Pan, "BoxRouter: A new global router based on box expansion and progressive ILP," in Proc. Des. Autom. Conf., 2006, pp. 373-378.
5. C. Sechen and A. Sangiovanni-Vincentelli, "The TimberWolf placement and routing package," IEEE J. Solid-State Circuits, vol. SSC-20, no. 2, pp. 510-522, Apr. 1985.
6. H. Shin and A. Sangiovanni-Vincentelli, "Mighty: A rip-up and reroute detailed router," in Proc. Int. Conf. Comput.-Aided Des., 1986, pp. 115-122.
7. L. E. Liu and C. Sechen, "Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 10, pp. 1442-1451, Oct. 1997.
8. J. A. Roy and I. L. Markov, "High performance routing at the nanometer scale," in Pmc. Int. Conf. Comput.-Aided Des., 2007, pp. 496-502.
9. M. Cho, K. Lu, K. Yuan, and D. Z. Pan, "BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router," in Proc. Int. Conf. Comput-Aided Des., 2007, pp. 503-508.
10. M. M. Ozdal and M. D. F. Wong, "Archer: A. history-driven global routing algorithm," in Proc. Int. Conf. Comput.-Aided Des., 2007, pp. 488-495.
11. M. D. Moffitt, "MaizeRouter: Engineering an effective global router," in Proc. Asia South Pacific Des. Autom. Confi, 2008, pp. 226-231.
12. M. J. Ciesielski, "Layer assignment for VLSI interconnect delay minimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 8, no. 6, pp. 702-707, Jun. 1989.
13. J. D. Cho, S. Raje, M. Sarrafzadeh, M. Sriram, and S. M. Kang, "Crosstalk-minimum, layer assignment," in Proc. Custom Integr. Circuits Conf., 1993, pp. 29.7.1-29.7.4.
14. D. Wu, J. Hu, R. Mahapatra, and M. Zhao, "Layer assignment for crosstalk risk minimization," in Proc. Asia South Pacific. Des. Autom. Confi., 2004, pp. 159-162.
15. ISPD 2007 Global Routing Contest. [Online]. Available: http://www. sigda.org/ispd2007/co.ntest.html
16. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2nd ed. New York: McGraw-Hill, 2001.
17. FGR 1.1. [Online]. Available: http://vlsicad.eecs.um.ich.edu/BK/FGR
18. K. Ahn and S. Sahni, "Constrained via minimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 2, pp. 273-282, Feb. 1993.
19. C. C. Chang and J. Cong, "An efficient approach to multilayer layer assignment with an application to via minimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 5, pp. 608-620, May 1999.
20. N. J. Naclerio, S. Masuda, and K. Nakajima, 'The via minimization, problem is NP-complete," IEEE Trans. Comput., vol. 38, no. 11, pp. 1604-1608, Nov. 1989.
21. K. C. Chang and H. C. Du, "Layer assignment problem for three-layer routing," IEEE Trans. Comput., vol. 37, no. 5, pp. 625-632, May 1988.
22. J. A. Roy, 2008. private communication.
23. J.-R. Gao, P.-C. Wu, and T-C Wang, "A new global router for modern designs," in Proc. Asia South Pacific Des. Autom. Confi, 2008, pp. 232-237.