Self-test techniques for crypto-devices

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 2, 2010, Pages 329-333

  Di Natale, Giorgio ^a   Doulcier, Marion ^a   Flottes, Marie Lise ^a   Rouzeyre, Bruno ^a  

^a LIRMM   (France)

Author keywords

Digital circuit testing; Security; Self testing

Indexed keywords

ALIASING; AREA OVERHEAD; FAULT COVERAGES; HOST DEVICES; PSEUDO-RANDOM TESTS; RESPONSE ANALYSIS; RESPONSE COMPACTION; SCAN CHAIN; SELF-TEST; SELF-TESTING; SYMMETRIC ENCRYPTION;

CRYPTOGRAPHY; DIGITAL INTEGRATED CIRCUITS; NETWORK SECURITY; TEST FACILITIES;

BUILT-IN SELF TEST;

EID: 75549090537     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2010045     Document Type: Article

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