On random pattern testability of cryptographic VLSI cores

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 3, 2000, Pages 185-192

  Schubert, Andreas ^a   Anheier, Walter ^a,b  

^a UNIVERSITY OF BREMEN   (Germany)

^b PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; CRYPTOGRAPHY; DATA FLOW ANALYSIS; DESIGN FOR TESTABILITY; PROBABILITY DISTRIBUTIONS; SHIFT REGISTERS; STATISTICAL METHODS;

CRYPTOGRAPHIC PROCESSOR CORES; DATA FLOW GRAPHS; PSEUDORANDOM PROPERTIES; RANDOM PATTERN TESTABILITY; SIGNATURE REGISTERS; SYMMETRIC BLOCK CIPHER; SYMMETRIC BLOCK ENCRYPTION ALGORITHMS;

VLSI CIRCUITS;

EID: 0033707340     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008378912411     Document Type: Article

References (6)

1. H. Bonnenberg, "Secure Testing of VLSI Cryptographic Equipment," Dissertation No. 10204, ETH Zurich, 1993.
2. Federal Information Processing Standard Publication (FIPS PUB) 140,"Telecommunications: General Security Requirements for Equipment using the Data Encryption Standard," USA, 1982.
3. M. Gerner, B. Müller, and G. Sandweg, Selbsttest digitaler Schaltungen, R. Oldenbourg Verlag, München, 1990.
4. B. Schneier, Applied Cryptography, Protocols, Algorithms, and Source Code in C, John Wiley & Sons, New York, 1994.
5. J. Daemen, R. Govaerts, and J. Vandewalle, "A New Approach to Block Cipher Design," Fast Software Encryption, Lectures Notes in Computer Science No. 809, Springer, New York, pp. 18-32, 1994.
6. P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, New York, 1987.