Circular BIST with state skipping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 5, 2002, Pages 668-672

  Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Built in self test (BIST); Built in testing; Circuit testing; Design for testability; Limit cycles; Pseudorandom pattern generation; Scan chains

Indexed keywords

BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; LOGIC CIRCUITS; LOGIC DESIGN; RANDOM PROCESSES;

CIRCULAR BUILT-IN SELF TEST; CONTROL LOGIC; PSEUDORANDOM PATTERN GENERATION; STATE SKIPPING LOGIC;

VLSI CIRCUITS;

EID: 0036818847     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.801564     Document Type: Article

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