Securing scan design using lock & key technique

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 51-59

  Lee, Jeremy ^a   Tehranipoor, Mohammed ^a   Patel, Chintan ^a   Plusquellic, Jim ^a  

^a UNIVERSITY OF MARYLAND BALTIMORE COUNTY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INSECURE MODE; SCAN DESIGN; SECURITY THREAT;

CONTROL EQUIPMENT; CONTROLLABILITY; MICROPROCESSOR CHIPS; OBSERVABILITY; SECURITY OF DATA; VLSI CIRCUITS;

SCANNING;

EID: 28444448348     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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