Low-power multiple-precision iterative floating-point multiplier with SIMD support

IEEE Transactions on Computers

Volumn 58, Issue 2, 2009, Pages 175-187

  Tan, Dimitri ^a   Lemonds, Carl E ^a   Schulte, Michael J ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Computer arithmetic; Floating point arithmetic; Low power; Multimedia; Multiplying circuits; Rectangular multiplier; Very large scale integration

Indexed keywords

BACKWARD COMPATIBILITY; COMBINED EFFECT; COMPUTER ARITHMETIC; DYNAMIC POWER DISSIPATION; FLOATING POINT UNITS; FLOATING-POINT ARITHMETIC; FLOATING-POINT INSTRUCTION; FOUR CYCLES; IEEE-754 STANDARD; LOW POWER; LOW-POWER COMPUTING; POINT MULTIPLIERS; POWER CONSUMPTION; SQUARE-ROOT; TRANSCENDENTAL FUNCTIONS; VERY-LARGE-SCALE INTEGRATION;

DIGITAL ARITHMETIC; FREQUENCY MULTIPLYING CIRCUITS; LSI CIRCUITS; MICROPROCESSOR CHIPS; NETWORK ROUTING;

MULTIPLYING CIRCUITS;

EID: 75449106575     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.203     Document Type: Article

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