A new architecture for multiple-precision floating-point multiply-add fused unit design

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2007, Pages 69-76

  Libo, Huang ^a   Li, Shen ^a   Kui, Dai ^a   Zhiying, Wang ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; LOGIC DESIGN; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS;

FLOATING-POINT MULTIPLY-ADD FUSED (MAF); MULTIMEDIA APPLICATIONS; PROCESSOR DESIGN; SINGLE INSTRUCTION MULTIPLE DATA (SIMD);

DIGITAL ARITHMETIC;

EID: 36049002227     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARITH.2007.5     Document Type: Conference Paper

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